/*
 * Copyright (c) [2020], MediaTek Inc. All rights reserved.
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. and/or its licensors.
 * Except as otherwise provided in the applicable licensing terms with
 * MediaTek Inc. and/or its licensors, any reproduction, modification, use or
 * disclosure of MediaTek Software, and information contained herein, in whole
 * or in part, shall be strictly prohibited.
*/
//[File]            : bn1_wf_agg_top.h
//[Revision time]   : Mon Jun 25 10:26:04 2018
//[Description]     : This file is auto generated by CODA
//[Copyright]       : Copyright (C) 2018 Mediatek Incorportion. All rights reserved.

#ifndef __BN1_WF_AGG_TOP_REGS_H__
#define __BN1_WF_AGG_TOP_REGS_H__

#include "hal_common.h"

#ifdef __cplusplus
extern "C" {
#endif


//****************************************************************************
//
//                     BN1_WF_AGG_TOP CR Definitions                     
//
//****************************************************************************

#define BN1_WF_AGG_TOP_BASE                                    0x820f2000

#define BN1_WF_AGG_TOP_BCR_ADDR                                (BN1_WF_AGG_TOP_BASE + 0x00) // 2000
#define BN1_WF_AGG_TOP_BWCR_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x04) // 2004
#define BN1_WF_AGG_TOP_TPCR_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x08) // 2008
#define BN1_WF_AGG_TOP_ARURCR_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x0c) // 200C
#define BN1_WF_AGG_TOP_ARDRCR_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x10) // 2010
#define BN1_WF_AGG_TOP_ARCR0_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x14) // 2014
#define BN1_WF_AGG_TOP_ARCR1_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x18) // 2018
#define BN1_WF_AGG_TOP_ARCR2_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x1c) // 201C
#define BN1_WF_AGG_TOP_ARUCR_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x20) // 2020
#define BN1_WF_AGG_TOP_ARDCR_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x24) // 2024
#define BN1_WF_AGG_TOP_FRM1RR0_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x28) // 2028
#define BN1_WF_AGG_TOP_FRM1RR1_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x2c) // 202C
#define BN1_WF_AGG_TOP_FRM1RR2_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x30) // 2030
#define BN1_WF_AGG_TOP_FRM1RR3_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x34) // 2034
#define BN1_WF_AGG_TOP_FRM1RR4_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x38) // 2038
#define BN1_WF_AGG_TOP_FRM1RR5_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x3c) // 203C
#define BN1_WF_AGG_TOP_FRM1RR6_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x40) // 2040
#define BN1_WF_AGG_TOP_FRM1RR7_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x44) // 2044
#define BN1_WF_AGG_TOP_AALCR0_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x48) // 2048
#define BN1_WF_AGG_TOP_AALCR1_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x4c) // 204C
#define BN1_WF_AGG_TOP_AALCR2_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x50) // 2050
#define BN1_WF_AGG_TOP_AALCR3_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x54) // 2054
#define BN1_WF_AGG_TOP_AALCR4_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x58) // 2058
#define BN1_WF_AGG_TOP_AWSCR0_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x5c) // 205C
#define BN1_WF_AGG_TOP_AWSCR1_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x60) // 2060
#define BN1_WF_AGG_TOP_AWSCR2_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x64) // 2064
#define BN1_WF_AGG_TOP_AWSCR3_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x68) // 2068
#define BN1_WF_AGG_TOP_PCR0_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x6c) // 206C
#define BN1_WF_AGG_TOP_PCR1_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x70) // 2070
#define BN1_WF_AGG_TOP_PCR3_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x74) // 2074
#define BN1_WF_AGG_TOP_PCR4_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x78) // 2078
#define BN1_WF_AGG_TOP_TTCR0_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x7c) // 207C
#define BN1_WF_AGG_TOP_TTCR1_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x80) // 2080
#define BN1_WF_AGG_TOP_ACR0_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x84) // 2084
#define BN1_WF_AGG_TOP_ACR1_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x88) // 2088
#define BN1_WF_AGG_TOP_ACR4_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x8c) // 208C
#define BN1_WF_AGG_TOP_ACR6_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x90) // 2090
#define BN1_WF_AGG_TOP_ACR7_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x94) // 2094
#define BN1_WF_AGG_TOP_MRCR_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x98) // 2098
#define BN1_WF_AGG_TOP_BTIMRR0_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x9c) // 209C
#define BN1_WF_AGG_TOP_BTIMRR1_ADDR                            (BN1_WF_AGG_TOP_BASE + 0xa0) // 20A0
#define BN1_WF_AGG_TOP_BTIMRR2_ADDR                            (BN1_WF_AGG_TOP_BASE + 0xa4) // 20A4
#define BN1_WF_AGG_TOP_BTIMRR3_ADDR                            (BN1_WF_AGG_TOP_BASE + 0xa8) // 20A8
#define BN1_WF_AGG_TOP_BTIMRR4_ADDR                            (BN1_WF_AGG_TOP_BASE + 0xac) // 20AC
#define BN1_WF_AGG_TOP_BTIMRR5_ADDR                            (BN1_WF_AGG_TOP_BASE + 0xb0) // 20B0
#define BN1_WF_AGG_TOP_BTIMRR6_ADDR                            (BN1_WF_AGG_TOP_BASE + 0xb4) // 20B4
#define BN1_WF_AGG_TOP_BTIMRR7_ADDR                            (BN1_WF_AGG_TOP_BASE + 0xb8) // 20B8
#define BN1_WF_AGG_TOP_BTIMRR8_ADDR                            (BN1_WF_AGG_TOP_BASE + 0xbc) // 20BC
#define BN1_WF_AGG_TOP_BTIMRR9_ADDR                            (BN1_WF_AGG_TOP_BASE + 0xc0) // 20C0
#define BN1_WF_AGG_TOP_LBCR_ADDR                               (BN1_WF_AGG_TOP_BASE + 0xc4) // 20C4
#define BN1_WF_AGG_TOP_MMPDR_ADDR                              (BN1_WF_AGG_TOP_BASE + 0xc8) // 20C8
#define BN1_WF_AGG_TOP_GFPDR_ADDR                              (BN1_WF_AGG_TOP_BASE + 0xcc) // 20CC
#define BN1_WF_AGG_TOP_VHTPDR_ADDR                             (BN1_WF_AGG_TOP_BASE + 0xd0) // 20D0
#define BN1_WF_AGG_TOP_HEPDR_ADDR                              (BN1_WF_AGG_TOP_BASE + 0xd4) // 20D4
#define BN1_WF_AGG_TOP_MUCR0_ADDR                              (BN1_WF_AGG_TOP_BASE + 0xd8) // 20D8
#define BN1_WF_AGG_TOP_MUCR1_ADDR                              (BN1_WF_AGG_TOP_BASE + 0xdc) // 20DC
#define BN1_WF_AGG_TOP_MURDGCR0_ADDR                           (BN1_WF_AGG_TOP_BASE + 0xe0) // 20E0
#define BN1_WF_AGG_TOP_MURDGCR1_ADDR                           (BN1_WF_AGG_TOP_BASE + 0xe4) // 20E4
#define BN1_WF_AGG_TOP_CTCR_ADDR                               (BN1_WF_AGG_TOP_BASE + 0xe8) // 20E8
#define BN1_WF_AGG_TOP_ATCR0_ADDR                              (BN1_WF_AGG_TOP_BASE + 0xec) // 20EC
#define BN1_WF_AGG_TOP_ATCR1_ADDR                              (BN1_WF_AGG_TOP_BASE + 0xf0) // 20F0
#define BN1_WF_AGG_TOP_ATCR3_ADDR                              (BN1_WF_AGG_TOP_BASE + 0xf4) // 20F4
#define BN1_WF_AGG_TOP_SRCR_ADDR                               (BN1_WF_AGG_TOP_BASE + 0xf8) // 20F8
#define BN1_WF_AGG_TOP_VBCR_ADDR                               (BN1_WF_AGG_TOP_BASE + 0xfc) // 20FC
#define BN1_WF_AGG_TOP_B0BRR0_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x100) // 2100
#define BN1_WF_AGG_TOP_B1BRR0_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x104) // 2104
#define BN1_WF_AGG_TOP_B2BRR0_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x108) // 2108
#define BN1_WF_AGG_TOP_B3BRR0_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x10c) // 210C
#define BN1_WF_AGG_TOP_TWTCR_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x110) // 2110
#define BN1_WF_AGG_TOP_TWTSTACR_ADDR                           (BN1_WF_AGG_TOP_BASE + 0x114) // 2114
#define BN1_WF_AGG_TOP_TWTE0TB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x118) // 2118
#define BN1_WF_AGG_TOP_TWTE1TB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x11c) // 211C
#define BN1_WF_AGG_TOP_TWTE2TB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x120) // 2120
#define BN1_WF_AGG_TOP_TWTE3TB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x124) // 2124
#define BN1_WF_AGG_TOP_TWTE4TB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x128) // 2128
#define BN1_WF_AGG_TOP_TWTE5TB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x12c) // 212C
#define BN1_WF_AGG_TOP_TWTE6TB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x130) // 2130
#define BN1_WF_AGG_TOP_TWTE7TB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x134) // 2134
#define BN1_WF_AGG_TOP_TWTE8TB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x138) // 2138
#define BN1_WF_AGG_TOP_TWTE9TB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x13c) // 213C
#define BN1_WF_AGG_TOP_TWTEATB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x140) // 2140
#define BN1_WF_AGG_TOP_TWTEBTB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x144) // 2144
#define BN1_WF_AGG_TOP_TWTECTB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x148) // 2148
#define BN1_WF_AGG_TOP_TWTEDTB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x14c) // 214C
#define BN1_WF_AGG_TOP_TWTEETB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x150) // 2150
#define BN1_WF_AGG_TOP_TWTEFTB_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x154) // 2154
#define BN1_WF_AGG_TOP_TCR_ADDR                                (BN1_WF_AGG_TOP_BASE + 0x158) // 2158
#define BN1_WF_AGG_TOP_DBRCR0_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x15c) // 215C
#define BN1_WF_AGG_TOP_DBRCR1_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x160) // 2160
#define BN1_WF_AGG_TOP_SRHS_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x164) // 2164
#define BN1_WF_AGG_TOP_TCSR0_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x168) // 2168
#define BN1_WF_AGG_TOP_TCSR1_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x16c) // 216C
#define BN1_WF_AGG_TOP_TCSR2_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x170) // 2170
#define BN1_WF_AGG_TOP_AICR0_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x174) // 2174
#define BN1_WF_AGG_TOP_AICR1_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x178) // 2178
#define BN1_WF_AGG_TOP_AICR2_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x17C) // 217C
#define BN1_WF_AGG_TOP_AICR3_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x180) // 2180
#define BN1_WF_AGG_TOP_AICR4_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x184) // 2184
#define BN1_WF_AGG_TOP_AICR5_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x188) // 2188
#define BN1_WF_AGG_TOP_AICR6_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x18C) // 218C
#define BN1_WF_AGG_TOP_AICR7_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x190) // 2190
#define BN1_WF_AGG_TOP_AICR8_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x194) // 2194
#define BN1_WF_AGG_TOP_AICR9_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x198) // 2198
#define BN1_WF_AGG_TOP_AICRA_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x19C) // 219C
#define BN1_WF_AGG_TOP_AICRB_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x200) // 2200
#define BN1_WF_AGG_TOP_AICRC_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x204) // 2204
#define BN1_WF_AGG_TOP_AICRD_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x208) // 2208
#define BN1_WF_AGG_TOP_AICRE_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x20C) // 220C
#define BN1_WF_AGG_TOP_AICRF_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x210) // 2210
#define BN1_WF_AGG_TOP_SCR_ADDR                                (BN1_WF_AGG_TOP_BASE + 0x214) // 2214
#define BN1_WF_AGG_TOP_SCR0_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x218) // 2218
#define BN1_WF_AGG_TOP_SCR1_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x21c) // 221C
#define BN1_WF_AGG_TOP_DYNSCR_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x220) // 2220
#define BN1_WF_AGG_TOP_DYNSSCR_ADDR                            (BN1_WF_AGG_TOP_BASE + 0x240) // 2240
#define BN1_WF_AGG_TOP_CTETCR_ADDR                             (BN1_WF_AGG_TOP_BASE + 0x260) // 2260
#define BN1_WF_AGG_TOP_TCCR_ADDR                               (BN1_WF_AGG_TOP_BASE + 0x264) // 2264
#define BN1_WF_AGG_TOP_DCR_ADDR                                (BN1_WF_AGG_TOP_BASE + 0x2e0) // 22E0
#define BN1_WF_AGG_TOP_SMDCR_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x2e4) // 22E4
#define BN1_WF_AGG_TOP_TXCMDSMCR_ADDR                          (BN1_WF_AGG_TOP_BASE + 0x2e8) // 22E8
#define BN1_WF_AGG_TOP_SMCR0_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x2f0) // 22F0
#define BN1_WF_AGG_TOP_SMCR1_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x2f4) // 22F4
#define BN1_WF_AGG_TOP_SMCR2_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x2f8) // 22F8
#define BN1_WF_AGG_TOP_SMCR3_ADDR                              (BN1_WF_AGG_TOP_BASE + 0x2fc) // 22FC




/* =====================================================================================

  ---BCR (0x820f2000 + 0x00)---

    BCN_BUSY0_EN[0]              - (RW) Beacon queue active will cause Wi-Fi busy and cannot enter sleep mode
                                     1'b0: Wi-Fi busy is independent of beacon queue active.
                                     1'b1: Beacon queue active will lead to Wi-Fi busy.
    BMC_BUSY0_EN[1]              - (RW) Broadcast queue active will cause Wi-Fi busy and cannot enter sleep mode
                                     1'b0: Wi-Fi busy is independent of broadcast queue active.
                                     1'b1: Broadcast queue active will lead to Wi-Fi busy.
    RESERVED2[2]                 - (RO) Reserved bits
    NBCN_BUSY_EN[3]              - (RW) NBCN queue active will cause Wi-Fi busy and cannot enter sleep mode
                                     1'b0: Wi-Fi busy is independent of beacon queue active.
                                     1'b1: NBCN queue active will lead to Wi-Fi busy.
    NAF_BUSY_EN[4]               - (RW) NAF queue active will cause Wi-Fi busy and cannot enter sleep mode
                                     1'b0: Wi-Fi busy is independent of beacon queue active.
                                     1'b1: NAF queue active will lead to Wi-Fi busy.
    RESERVED5[14..5]             - (RO) Reserved bits
    QUE_BUSY0_SEL[15]            - (RW) Selects queue busy source
                                     1'b0: Wi-Fi cannot enter sleep mode if any queue is not empty.
                                     1'b1: Wi-Fi cannot enter sleep mode if any queue is not empty and enabled, which means that even a certain queue is not empty but SW disables this queue, we can still enter sleep mode.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_BCR_QUE_BUSY0_SEL_ADDR                  BN1_WF_AGG_TOP_BCR_ADDR
#define BN1_WF_AGG_TOP_BCR_QUE_BUSY0_SEL_MASK                  0x00008000                // QUE_BUSY0_SEL[15]
#define BN1_WF_AGG_TOP_BCR_QUE_BUSY0_SEL_SHFT                  15
#define BN1_WF_AGG_TOP_BCR_NAF_BUSY_EN_ADDR                    BN1_WF_AGG_TOP_BCR_ADDR
#define BN1_WF_AGG_TOP_BCR_NAF_BUSY_EN_MASK                    0x00000010                // NAF_BUSY_EN[4]
#define BN1_WF_AGG_TOP_BCR_NAF_BUSY_EN_SHFT                    4
#define BN1_WF_AGG_TOP_BCR_NBCN_BUSY_EN_ADDR                   BN1_WF_AGG_TOP_BCR_ADDR
#define BN1_WF_AGG_TOP_BCR_NBCN_BUSY_EN_MASK                   0x00000008                // NBCN_BUSY_EN[3]
#define BN1_WF_AGG_TOP_BCR_NBCN_BUSY_EN_SHFT                   3
#define BN1_WF_AGG_TOP_BCR_BMC_BUSY0_EN_ADDR                   BN1_WF_AGG_TOP_BCR_ADDR
#define BN1_WF_AGG_TOP_BCR_BMC_BUSY0_EN_MASK                   0x00000002                // BMC_BUSY0_EN[1]
#define BN1_WF_AGG_TOP_BCR_BMC_BUSY0_EN_SHFT                   1
#define BN1_WF_AGG_TOP_BCR_BCN_BUSY0_EN_ADDR                   BN1_WF_AGG_TOP_BCR_ADDR
#define BN1_WF_AGG_TOP_BCR_BCN_BUSY0_EN_MASK                   0x00000001                // BCN_BUSY0_EN[0]
#define BN1_WF_AGG_TOP_BCR_BCN_BUSY0_EN_SHFT                   0

/* =====================================================================================

  ---BWCR (0x820f2000 + 0x04)---

    PCO_PHASE0[0]                - (RW) PCO phase
                                     Valid only when PCO_ACTIVE0 and RF_BW0 >= 1.
                                     1'b0: 20M phase, TX PPDU bandwidth is 20M
                                     1'b1: 40M phase, TX PPDU bandwidth is 40M. If the RA of a frame indicates a peer with only 20M bandwidth capability, this frame will not be transmitted until PCO 20M phase.
    PCO_ACTIVE0[1]               - (RW) 1'b0: PCO not active; the actual TX PPDU bandwidth depends on WLAN entry peer frequency capability (FCAP), 20/40 backoff result.
                                     1'b1: PCO active (effective only if RF_BW0 >= 1); the TX PPDU bandwidth should follow PCO_PHASE0.
    RF_BW0[3..2]                 - (RW) RF bandwidth operating mode
                                     2'h0: 20MHz, RF operates at 20MHz
                                     2'h1: 40MHz, RF operates at 40MHz
                                     2'h2: 80MHz, RF operates at 80MHz
                                     2'h3: 160MHz, RF operates at 160MHz or 80+80MHz
    RESERVED4[4]                 - (RO) Reserved bits
    HONOR_CFP_DURREMAINING[5]    - (RW) CFP Dur Remaining honoring rule
                                     1'b0: Ignore honoring the CFP Dur Remaining (there exist APs that do not issue CFP DurRemaining correctly. Normally this setting will not be used.)
                                     1'b1: Honor the CFP Dur Remaining
    RESERVED6[14..6]             - (RO) Reserved bits
    MCS32_TO_0_EN[15]            - (RW) Enables HW auto change MCS32 as MCS0 when PCO or TXOP's bandwidth is 20M
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_BWCR_MCS32_TO_0_EN_ADDR                 BN1_WF_AGG_TOP_BWCR_ADDR
#define BN1_WF_AGG_TOP_BWCR_MCS32_TO_0_EN_MASK                 0x00008000                // MCS32_TO_0_EN[15]
#define BN1_WF_AGG_TOP_BWCR_MCS32_TO_0_EN_SHFT                 15
#define BN1_WF_AGG_TOP_BWCR_HONOR_CFP_DURREMAINING_ADDR        BN1_WF_AGG_TOP_BWCR_ADDR
#define BN1_WF_AGG_TOP_BWCR_HONOR_CFP_DURREMAINING_MASK        0x00000020                // HONOR_CFP_DURREMAINING[5]
#define BN1_WF_AGG_TOP_BWCR_HONOR_CFP_DURREMAINING_SHFT        5
#define BN1_WF_AGG_TOP_BWCR_RF_BW0_ADDR                        BN1_WF_AGG_TOP_BWCR_ADDR
#define BN1_WF_AGG_TOP_BWCR_RF_BW0_MASK                        0x0000000C                // RF_BW0[3..2]
#define BN1_WF_AGG_TOP_BWCR_RF_BW0_SHFT                        2
#define BN1_WF_AGG_TOP_BWCR_PCO_ACTIVE0_ADDR                   BN1_WF_AGG_TOP_BWCR_ADDR
#define BN1_WF_AGG_TOP_BWCR_PCO_ACTIVE0_MASK                   0x00000002                // PCO_ACTIVE0[1]
#define BN1_WF_AGG_TOP_BWCR_PCO_ACTIVE0_SHFT                   1
#define BN1_WF_AGG_TOP_BWCR_PCO_PHASE0_ADDR                    BN1_WF_AGG_TOP_BWCR_ADDR
#define BN1_WF_AGG_TOP_BWCR_PCO_PHASE0_MASK                    0x00000001                // PCO_PHASE0[0]
#define BN1_WF_AGG_TOP_BWCR_PCO_PHASE0_SHFT                    0

/* =====================================================================================

  ---TPCR (0x820f2000 + 0x08)---

    TXOP_PS_EN0[0]               - (RW) Enables TXOP PS for BSS0
                                     1'b1: For AP, TXOP_PS_NOT_ALLOWED may be cleared
                                     1'b0: Disable above function
    TXOP_PS_EN1[1]               - (RW) Enables TXOP PS for BSS1
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN2[2]               - (RW) Enables TXOP PS for BSS2
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN3[3]               - (RW) Enables TXOP PS for BSS3.
                                     Same as TXOP_PS_EN0.
    RESERVED4[14..4]             - (RO) Reserved bits
    TXOP_PS_NAV_FORCE_MD[15]     - (RW) When Tx a long NAV with TXOP_PS_NOT_ALLOW = 0, force MD bit to 1.
    RESERVED16[16]               - (RO) Reserved bits
    TXOP_PS_EN0_1[17]            - (RW) Enables TXOP_PS for sub-BSS1 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_2[18]            - (RW) Enables TXOP_PS for sub-BSS2 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_3[19]            - (RW) Enables TXOP_PS for sub-BSS3 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_4[20]            - (RW) Enables TXOP_PS for sub-BSS4 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_5[21]            - (RW) Enables TXOP_PS for sub-BSS5 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_6[22]            - (RW) Enables TXOP_PS for sub-BSS6 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_7[23]            - (RW) Enables TXOP_PS for sub-BSS7 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_8[24]            - (RW) Enables TXOP_PS for sub-BSS8 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_9[25]            - (RW) Enables TXOP_PS for sub-BSS9 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_10[26]           - (RW) Enables TXOP_PS for sub-BSS10 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_11[27]           - (RW) Enables TXOP_PS for sub-BSS11 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_12[28]           - (RW) Enables TXOP_PS for sub-BSS12 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_13[29]           - (RW) Enables TXOP_PS for sub-BSS13 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_14[30]           - (RW) Enables TXOP_PS for sub-BSS14 of BSS0
                                     Same as TXOP_PS_EN0.
    TXOP_PS_EN0_15[31]           - (RW) Enables TXOP_PS for sub-BSS15 of BSS0
                                     Same as TXOP_PS_EN0.

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_15_ADDR                BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_15_MASK                0x80000000                // TXOP_PS_EN0_15[31]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_15_SHFT                31
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_14_ADDR                BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_14_MASK                0x40000000                // TXOP_PS_EN0_14[30]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_14_SHFT                30
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_13_ADDR                BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_13_MASK                0x20000000                // TXOP_PS_EN0_13[29]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_13_SHFT                29
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_12_ADDR                BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_12_MASK                0x10000000                // TXOP_PS_EN0_12[28]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_12_SHFT                28
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_11_ADDR                BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_11_MASK                0x08000000                // TXOP_PS_EN0_11[27]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_11_SHFT                27
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_10_ADDR                BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_10_MASK                0x04000000                // TXOP_PS_EN0_10[26]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_10_SHFT                26
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_9_ADDR                 BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_9_MASK                 0x02000000                // TXOP_PS_EN0_9[25]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_9_SHFT                 25
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_8_ADDR                 BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_8_MASK                 0x01000000                // TXOP_PS_EN0_8[24]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_8_SHFT                 24
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_7_ADDR                 BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_7_MASK                 0x00800000                // TXOP_PS_EN0_7[23]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_7_SHFT                 23
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_6_ADDR                 BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_6_MASK                 0x00400000                // TXOP_PS_EN0_6[22]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_6_SHFT                 22
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_5_ADDR                 BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_5_MASK                 0x00200000                // TXOP_PS_EN0_5[21]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_5_SHFT                 21
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_4_ADDR                 BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_4_MASK                 0x00100000                // TXOP_PS_EN0_4[20]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_4_SHFT                 20
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_3_ADDR                 BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_3_MASK                 0x00080000                // TXOP_PS_EN0_3[19]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_3_SHFT                 19
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_2_ADDR                 BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_2_MASK                 0x00040000                // TXOP_PS_EN0_2[18]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_2_SHFT                 18
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_1_ADDR                 BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_1_MASK                 0x00020000                // TXOP_PS_EN0_1[17]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_1_SHFT                 17
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_NAV_FORCE_MD_ADDR          BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_NAV_FORCE_MD_MASK          0x00008000                // TXOP_PS_NAV_FORCE_MD[15]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_NAV_FORCE_MD_SHFT          15
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN3_ADDR                   BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN3_MASK                   0x00000008                // TXOP_PS_EN3[3]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN3_SHFT                   3
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN2_ADDR                   BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN2_MASK                   0x00000004                // TXOP_PS_EN2[2]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN2_SHFT                   2
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN1_ADDR                   BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN1_MASK                   0x00000002                // TXOP_PS_EN1[1]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN1_SHFT                   1
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_ADDR                   BN1_WF_AGG_TOP_TPCR_ADDR
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_MASK                   0x00000001                // TXOP_PS_EN0[0]
#define BN1_WF_AGG_TOP_TPCR_TXOP_PS_EN0_SHFT                   0

/* =====================================================================================

  ---ARURCR (0x820f2000 + 0x0c)---

    RATE1_UP_RATE[2..0]          - (RW) Rate 1 up rate index. Indicate next rate index when rate up from rate 1. Default value is 0(rate 1).
    RESERVED3[3]                 - (RO) Reserved bits
    RATE2_UP_RATE[6..4]          - (RW) Rate 2 up rate index. Indicate next rate index when rate up from rate 2. Default value is 0(rate 1).
    RESERVED7[7]                 - (RO) Reserved bits
    RATE3_UP_RATE[10..8]         - (RW) Rate 3 up rate index. Indicate next rate index when rate up from rate 3. Default value is 1(rate 2).
    RESERVED11[11]               - (RO) Reserved bits
    RATE4_UP_RATE[14..12]        - (RW) Rate 4 up rate index. Indicate next rate index when rate up from rate 4. Default value is 1(rate 2).
    RESERVED15[15]               - (RO) Reserved bits
    RATE5_UP_RATE[18..16]        - (RW) Rate 5 up rate index. Indicate next rate index when rate up from rate 5. Default value is 3(rate 4).
    RESERVED19[19]               - (RO) Reserved bits
    RATE6_UP_RATE[22..20]        - (RW) Rate 6 up rate index. Indicate next rate index when rate up from rate 6. Default value is 3(rate 4).
    RESERVED23[23]               - (RO) Reserved bits
    RATE7_UP_RATE[26..24]        - (RW) Rate 7 up rate index. Indicate next rate index when rate up from rate 7. Default value is 3(rate 4).
    RESERVED27[27]               - (RO) Reserved bits
    RATE8_UP_RATE[30..28]        - (RW) Rate 8 up rate index. Indicate next rate index when rate up from rate 8. Default value is 3(rate 4).
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ARURCR_RATE8_UP_RATE_ADDR               BN1_WF_AGG_TOP_ARURCR_ADDR
#define BN1_WF_AGG_TOP_ARURCR_RATE8_UP_RATE_MASK               0x70000000                // RATE8_UP_RATE[30..28]
#define BN1_WF_AGG_TOP_ARURCR_RATE8_UP_RATE_SHFT               28
#define BN1_WF_AGG_TOP_ARURCR_RATE7_UP_RATE_ADDR               BN1_WF_AGG_TOP_ARURCR_ADDR
#define BN1_WF_AGG_TOP_ARURCR_RATE7_UP_RATE_MASK               0x07000000                // RATE7_UP_RATE[26..24]
#define BN1_WF_AGG_TOP_ARURCR_RATE7_UP_RATE_SHFT               24
#define BN1_WF_AGG_TOP_ARURCR_RATE6_UP_RATE_ADDR               BN1_WF_AGG_TOP_ARURCR_ADDR
#define BN1_WF_AGG_TOP_ARURCR_RATE6_UP_RATE_MASK               0x00700000                // RATE6_UP_RATE[22..20]
#define BN1_WF_AGG_TOP_ARURCR_RATE6_UP_RATE_SHFT               20
#define BN1_WF_AGG_TOP_ARURCR_RATE5_UP_RATE_ADDR               BN1_WF_AGG_TOP_ARURCR_ADDR
#define BN1_WF_AGG_TOP_ARURCR_RATE5_UP_RATE_MASK               0x00070000                // RATE5_UP_RATE[18..16]
#define BN1_WF_AGG_TOP_ARURCR_RATE5_UP_RATE_SHFT               16
#define BN1_WF_AGG_TOP_ARURCR_RATE4_UP_RATE_ADDR               BN1_WF_AGG_TOP_ARURCR_ADDR
#define BN1_WF_AGG_TOP_ARURCR_RATE4_UP_RATE_MASK               0x00007000                // RATE4_UP_RATE[14..12]
#define BN1_WF_AGG_TOP_ARURCR_RATE4_UP_RATE_SHFT               12
#define BN1_WF_AGG_TOP_ARURCR_RATE3_UP_RATE_ADDR               BN1_WF_AGG_TOP_ARURCR_ADDR
#define BN1_WF_AGG_TOP_ARURCR_RATE3_UP_RATE_MASK               0x00000700                // RATE3_UP_RATE[10..8]
#define BN1_WF_AGG_TOP_ARURCR_RATE3_UP_RATE_SHFT               8
#define BN1_WF_AGG_TOP_ARURCR_RATE2_UP_RATE_ADDR               BN1_WF_AGG_TOP_ARURCR_ADDR
#define BN1_WF_AGG_TOP_ARURCR_RATE2_UP_RATE_MASK               0x00000070                // RATE2_UP_RATE[6..4]
#define BN1_WF_AGG_TOP_ARURCR_RATE2_UP_RATE_SHFT               4
#define BN1_WF_AGG_TOP_ARURCR_RATE1_UP_RATE_ADDR               BN1_WF_AGG_TOP_ARURCR_ADDR
#define BN1_WF_AGG_TOP_ARURCR_RATE1_UP_RATE_MASK               0x00000007                // RATE1_UP_RATE[2..0]
#define BN1_WF_AGG_TOP_ARURCR_RATE1_UP_RATE_SHFT               0

/* =====================================================================================

  ---ARDRCR (0x820f2000 + 0x10)---

    RATE1_DOWN_RATE[2..0]        - (RW) Rate 1 down rate index. Indicate next rate index when rate down from rate 1. Default value is 1(rate 2).
    RESERVED3[3]                 - (RO) Reserved bits
    RATE2_DOWN_RATE[6..4]        - (RW) Rate 2 down rate index. Indicate next rate index when rate down from rate 2. Default value is 2(rate 3).
    RESERVED7[7]                 - (RO) Reserved bits
    RATE3_DOWN_RATE[10..8]       - (RW) Rate 3 down rate index. Indicate next rate index when rate down from rate 3. Default value is 3(rate 4).
    RESERVED11[11]               - (RO) Reserved bits
    RATE4_DOWN_RATE[14..12]      - (RW) Rate 4 down rate index. Indicate next rate index when rate down from rate 4. Default value is 4(rate 5).
    RESERVED15[15]               - (RO) Reserved bits
    RATE5_DOWN_RATE[18..16]      - (RW) Rate 5 down rate index. Indicate next rate index when rate down from rate 5. Default value is 5(rate 6).
    RESERVED19[19]               - (RO) Reserved bits
    RATE6_DOWN_RATE[22..20]      - (RW) Rate 6 down rate index. Indicate next rate index when rate down from rate 6. Default value is 6(rate 7).
    RESERVED23[23]               - (RO) Reserved bits
    RATE7_DOWN_RATE[26..24]      - (RW) Rate 7 down rate index. Indicate next rate index when rate down from rate 7. Default value is 7(rate 8).
    RESERVED27[27]               - (RO) Reserved bits
    RATE8_DOWN_RATE[30..28]      - (RW) Rate 8 down rate index. Indicate next rate index when rate down from rate 8. Default value is 7(rate 8).
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ARDRCR_RATE8_DOWN_RATE_ADDR             BN1_WF_AGG_TOP_ARDRCR_ADDR
#define BN1_WF_AGG_TOP_ARDRCR_RATE8_DOWN_RATE_MASK             0x70000000                // RATE8_DOWN_RATE[30..28]
#define BN1_WF_AGG_TOP_ARDRCR_RATE8_DOWN_RATE_SHFT             28
#define BN1_WF_AGG_TOP_ARDRCR_RATE7_DOWN_RATE_ADDR             BN1_WF_AGG_TOP_ARDRCR_ADDR
#define BN1_WF_AGG_TOP_ARDRCR_RATE7_DOWN_RATE_MASK             0x07000000                // RATE7_DOWN_RATE[26..24]
#define BN1_WF_AGG_TOP_ARDRCR_RATE7_DOWN_RATE_SHFT             24
#define BN1_WF_AGG_TOP_ARDRCR_RATE6_DOWN_RATE_ADDR             BN1_WF_AGG_TOP_ARDRCR_ADDR
#define BN1_WF_AGG_TOP_ARDRCR_RATE6_DOWN_RATE_MASK             0x00700000                // RATE6_DOWN_RATE[22..20]
#define BN1_WF_AGG_TOP_ARDRCR_RATE6_DOWN_RATE_SHFT             20
#define BN1_WF_AGG_TOP_ARDRCR_RATE5_DOWN_RATE_ADDR             BN1_WF_AGG_TOP_ARDRCR_ADDR
#define BN1_WF_AGG_TOP_ARDRCR_RATE5_DOWN_RATE_MASK             0x00070000                // RATE5_DOWN_RATE[18..16]
#define BN1_WF_AGG_TOP_ARDRCR_RATE5_DOWN_RATE_SHFT             16
#define BN1_WF_AGG_TOP_ARDRCR_RATE4_DOWN_RATE_ADDR             BN1_WF_AGG_TOP_ARDRCR_ADDR
#define BN1_WF_AGG_TOP_ARDRCR_RATE4_DOWN_RATE_MASK             0x00007000                // RATE4_DOWN_RATE[14..12]
#define BN1_WF_AGG_TOP_ARDRCR_RATE4_DOWN_RATE_SHFT             12
#define BN1_WF_AGG_TOP_ARDRCR_RATE3_DOWN_RATE_ADDR             BN1_WF_AGG_TOP_ARDRCR_ADDR
#define BN1_WF_AGG_TOP_ARDRCR_RATE3_DOWN_RATE_MASK             0x00000700                // RATE3_DOWN_RATE[10..8]
#define BN1_WF_AGG_TOP_ARDRCR_RATE3_DOWN_RATE_SHFT             8
#define BN1_WF_AGG_TOP_ARDRCR_RATE2_DOWN_RATE_ADDR             BN1_WF_AGG_TOP_ARDRCR_ADDR
#define BN1_WF_AGG_TOP_ARDRCR_RATE2_DOWN_RATE_MASK             0x00000070                // RATE2_DOWN_RATE[6..4]
#define BN1_WF_AGG_TOP_ARDRCR_RATE2_DOWN_RATE_SHFT             4
#define BN1_WF_AGG_TOP_ARDRCR_RATE1_DOWN_RATE_ADDR             BN1_WF_AGG_TOP_ARDRCR_ADDR
#define BN1_WF_AGG_TOP_ARDRCR_RATE1_DOWN_RATE_MASK             0x00000007                // RATE1_DOWN_RATE[2..0]
#define BN1_WF_AGG_TOP_ARDRCR_RATE1_DOWN_RATE_SHFT             0

/* =====================================================================================

  ---ARCR0 (0x820f2000 + 0x14)---

    INI_RATE1[0]                 - (RW) Initial Rate 1
                                     1'b1: Use Rate 1 for the next PPDU when the first frame in the queue is released.
                                     1'b0: By original rate up and down rule
    FB_SGI_DIS[1]                - (RW) Disables fallback short GI
                                     0: For Rate 2~8, use short GI if WTBL indicates it.
                                     1: For Rate 2~8, not use short GI even WTBL indicates it. 
                                     (For Rate 1, always use short GI if WTBL indicates it.)
    INI_RATE1_MODE[2]            - (RW) Initial Rate 1 Mode (Active when INI_RATE1 set to 1)
                                     1'b1: Use Rate 1 for the next PPDU when any frame in the queue is released
                                     1'b0: Use Rate 1 for the next PPDU when the first frame in the queue is released
    SRWIN_AR_EN[3]               - (RW) Allow auto rate calaulation during spatial reuse window.
                                     1: Enable
                                     0: Disable
    RESERVED4[7..4]              - (RO) Reserved bits
    RTS_RATE_DOWN_TH[12..8]      - (RW) RTS rate down threshold 
                                     RTS will down rate after its RTS fail count is more than this threshold.
                                     5'd0: RTS will down rate after 1 fail.
                                     5'd1: RTS will down rate after 2 fail.
                                     ...
                                     5'd30: RTS will dwon rate after 31 fail.
                                     5'd31: RTS will dwon rate after 32 fail (but even RTS_RTY_CNT_LIMIT=31, this packet will drop, no down rate requirement).
    RESERVED13[15..13]           - (RO) Reserved bits
    RATE_DOWN_EXTRA_RATIO[17..16] - (RW) When RATE*_DOWN_LIMIT is reached, it will still keep the original rate and will not rate down if the  following extra ratio conditions are met.
                                     2'h0: Tx OK count >= Tx fail count
                                     2'h1: Tx OK count >= 2*Tx fail count
                                     2'h2: Tx OK count >= 4*Tx fail count
                                     2'h3: Tx OK count >= 8*Tx fail count
                                     Note: Tx OK/fail count will always be cleared no matter the extra ratio condition is met or not.
                                     Note: Only valid when RATE_DOWN_EXTRA_RATIO_EN = 1.
    RESERVED18[18]               - (RO) Reserved bits
    RATE_DOWN_EXTRA_RATIO_EN[19] - (RW) When RATE*_DOWN_LIMIT is reached, it has extra condition (RATE_DOWN_EXTRA_RATIO) to determine to rate down or not.
                                     1'b0: Always rate down when RATE*_DOWN_LIMIT is reached
                                     1'b1: Depend on RATE_DOWN_EXTRA_RATIO
                                     Note: Tx OK/fail count will always be cleared no matter the extra ratio condition is met or not.
    RATE_UP_EXTRA_TH[22..20]     - (RW) When RATE*_UP_LIMIT is reached, it will still keep the  original rate and will not rate up if the following extra threshold conditions are met.
                                     3'h0: Tx fail count >= 3'h1
                                     3'h1: Tx fail count >= 3'h2
                                     3'h2: Tx fail count >= 3'h3
                                     3'h3: Tx fail count >= 3'h4
                                     3'h4: Tx fail count >= 3'h5
                                     3'h5: Tx fail count >= 3'h6
                                     3'h6: Tx fail count >= 3'h7
                                     3'h7: Tx fail count >= 3'h8 (always rate up)
                                     Note: Tx OK/fail count will always be cleared no matter the extra threshold condition is met or not.
    RESERVED23[23]               - (RO) Reserved bits
    DS_DMCS_TH[26..24]           - (RW) Dynamic Sounding Delta MCS Threshold for SU. If next rate index >= this threshold, HW could assert interrupt for SW reference. Valid when DYNSCR is set.
    RESERVED27[30..27]           - (RO) Reserved bits
    DUAL_BTIM_EN[31]             - (RW) Enables dual TIM broadcast
                                     1'b0: Disable dual TIM broadcast mode. SW should allocate 2 TXD for dual BTIM requirement.
                                     1'b1: Enable dual TIM broadcast mode. SW only needs to allocate 1 TXD for dual BTIM requirement.

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ARCR0_DUAL_BTIM_EN_ADDR                 BN1_WF_AGG_TOP_ARCR0_ADDR
#define BN1_WF_AGG_TOP_ARCR0_DUAL_BTIM_EN_MASK                 0x80000000                // DUAL_BTIM_EN[31]
#define BN1_WF_AGG_TOP_ARCR0_DUAL_BTIM_EN_SHFT                 31
#define BN1_WF_AGG_TOP_ARCR0_DS_DMCS_TH_ADDR                   BN1_WF_AGG_TOP_ARCR0_ADDR
#define BN1_WF_AGG_TOP_ARCR0_DS_DMCS_TH_MASK                   0x07000000                // DS_DMCS_TH[26..24]
#define BN1_WF_AGG_TOP_ARCR0_DS_DMCS_TH_SHFT                   24
#define BN1_WF_AGG_TOP_ARCR0_RATE_UP_EXTRA_TH_ADDR             BN1_WF_AGG_TOP_ARCR0_ADDR
#define BN1_WF_AGG_TOP_ARCR0_RATE_UP_EXTRA_TH_MASK             0x00700000                // RATE_UP_EXTRA_TH[22..20]
#define BN1_WF_AGG_TOP_ARCR0_RATE_UP_EXTRA_TH_SHFT             20
#define BN1_WF_AGG_TOP_ARCR0_RATE_DOWN_EXTRA_RATIO_EN_ADDR     BN1_WF_AGG_TOP_ARCR0_ADDR
#define BN1_WF_AGG_TOP_ARCR0_RATE_DOWN_EXTRA_RATIO_EN_MASK     0x00080000                // RATE_DOWN_EXTRA_RATIO_EN[19]
#define BN1_WF_AGG_TOP_ARCR0_RATE_DOWN_EXTRA_RATIO_EN_SHFT     19
#define BN1_WF_AGG_TOP_ARCR0_RATE_DOWN_EXTRA_RATIO_ADDR        BN1_WF_AGG_TOP_ARCR0_ADDR
#define BN1_WF_AGG_TOP_ARCR0_RATE_DOWN_EXTRA_RATIO_MASK        0x00030000                // RATE_DOWN_EXTRA_RATIO[17..16]
#define BN1_WF_AGG_TOP_ARCR0_RATE_DOWN_EXTRA_RATIO_SHFT        16
#define BN1_WF_AGG_TOP_ARCR0_RTS_RATE_DOWN_TH_ADDR             BN1_WF_AGG_TOP_ARCR0_ADDR
#define BN1_WF_AGG_TOP_ARCR0_RTS_RATE_DOWN_TH_MASK             0x00001F00                // RTS_RATE_DOWN_TH[12..8]
#define BN1_WF_AGG_TOP_ARCR0_RTS_RATE_DOWN_TH_SHFT             8
#define BN1_WF_AGG_TOP_ARCR0_SRWIN_AR_EN_ADDR                  BN1_WF_AGG_TOP_ARCR0_ADDR
#define BN1_WF_AGG_TOP_ARCR0_SRWIN_AR_EN_MASK                  0x00000008                // SRWIN_AR_EN[3]
#define BN1_WF_AGG_TOP_ARCR0_SRWIN_AR_EN_SHFT                  3
#define BN1_WF_AGG_TOP_ARCR0_INI_RATE1_MODE_ADDR               BN1_WF_AGG_TOP_ARCR0_ADDR
#define BN1_WF_AGG_TOP_ARCR0_INI_RATE1_MODE_MASK               0x00000004                // INI_RATE1_MODE[2]
#define BN1_WF_AGG_TOP_ARCR0_INI_RATE1_MODE_SHFT               2
#define BN1_WF_AGG_TOP_ARCR0_FB_SGI_DIS_ADDR                   BN1_WF_AGG_TOP_ARCR0_ADDR
#define BN1_WF_AGG_TOP_ARCR0_FB_SGI_DIS_MASK                   0x00000002                // FB_SGI_DIS[1]
#define BN1_WF_AGG_TOP_ARCR0_FB_SGI_DIS_SHFT                   1
#define BN1_WF_AGG_TOP_ARCR0_INI_RATE1_ADDR                    BN1_WF_AGG_TOP_ARCR0_ADDR
#define BN1_WF_AGG_TOP_ARCR0_INI_RATE1_MASK                    0x00000001                // INI_RATE1[0]
#define BN1_WF_AGG_TOP_ARCR0_INI_RATE1_SHFT                    0

/* =====================================================================================

  ---ARCR1 (0x820f2000 + 0x18)---

    AMSDU_RATE[9..0]             - (RW) If the current packet is AMSDU and WTBL's auto rate is legacy rate (legacy OFDM or CCK), HW will apply AMSDU_RATE to transmit this packet,
                                     Assume STBC = 0 and Nsts = 0.
                                     Bit[9:6]: TX mode
                                     Indicates the transmission mode
                                     4'b0000: Legacy CCK  001: Legacy OFDM
                                     4'b0010: HT mixed mode  011: HT green field mode
                                     4'b0100: VHT mode
                                     4'b1000: HE_SU
                                     4'b1001: HE_EXT_SU
                                     4'b1010: HE_TRIG
                                     4'b1011: HE_MU
                                     1100~1111: reserved
                                     Bit[5:0]: TX rate
                                     For Legacy CCK:
                                     CCK: (long preamble)
                                     6'b00_0000: 1M   6'b00_0001: 2M
                                     6'b00_0010: 5.5M  6'b00_0011: 11M
                                     CCK: (short preamble)
                                     6'b00_0101: 2M   6'b00_0110: 5.5M
                                     6'b00_0111: 11M  
                                     For Legacy OFDM:
                                     6'b00_1011: 6M (in 20MHz channel spacing)
                                     6'b00_1111: 9M (in 20MHz channel spacing)
                                     6'b00_1010: 12M (in 20MHz channel spacing)
                                     6'b00_1110: 18M (in 20MHz channel spacing)
                                     6'b00_1001: 24M (in 20MHz channel spacing)
                                     6'b00_1101: 36M (in 20MHz channel spacing)
                                     6'b00_1000: 48M (in 20MHz channel spacing)
                                     6'b00_1100: 54M (in 20MHz channel spacing)
                                     For HT rate:
                                     Bit0~5 indicate MCSN, N=0~32; others reserved.
                                     For VHT rate:
                                     Bit0~5 indicate MCSN, N=0~9; others reserved.
                                     For HE rate:
                                     Bit0~3 indicate MCSN, N=0~11; others reserved.
    RESERVED10[15..10]           - (RO) Reserved bits
    AMSDU_GF_6M_TH[29..16]       - (RW) If Tx AMSDU, TXD's data length > AMSDU_GF_6M_TH, and the following conditions are met: 
                                       Green field, MCS32, force Tx rate to be MCS1.
                                       Green field, MCS0, force Tx rate to be MCS1.
                                     (9968us (MAX_GF_PSDU_DUR0~1)*6/8 bits = 7476 bytes)
                                     (7476 - 36 (MAC header) - 34 (cipher) - 4 (FCS) - 36 (RDGBA) -4 (delimiter) = 7362)
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ARCR1_AMSDU_GF_6M_TH_ADDR               BN1_WF_AGG_TOP_ARCR1_ADDR
#define BN1_WF_AGG_TOP_ARCR1_AMSDU_GF_6M_TH_MASK               0x3FFF0000                // AMSDU_GF_6M_TH[29..16]
#define BN1_WF_AGG_TOP_ARCR1_AMSDU_GF_6M_TH_SHFT               16
#define BN1_WF_AGG_TOP_ARCR1_AMSDU_RATE_ADDR                   BN1_WF_AGG_TOP_ARCR1_ADDR
#define BN1_WF_AGG_TOP_ARCR1_AMSDU_RATE_MASK                   0x000003FF                // AMSDU_RATE[9..0]
#define BN1_WF_AGG_TOP_ARCR1_AMSDU_RATE_SHFT                   0

/* =====================================================================================

  ---ARCR2 (0x820f2000 + 0x1c)---

    AMSDU_MM_6M_TH[13..0]        - (RW) If Tx AMSDU, TXD's data length > AMSDU_MM_6M_TH, and the following conditions are met:
                                       BW20, mix mode, MCS32, force Tx rate to be MCS1 (and AMSDU_MM_13M_TH not met).
                                       BW20, mix mode, MCS0, force Tx rate to be MCS1 (and AMSDU_MM_13M_TH not met).
                                       BW20, VHT, Nss=1, MCS0, force Tx rate to be MCS1 (and AMSDU_MM_13M_TH not met).
                                     (5440us (MAX_VHT_PSDU_DUR0~1)*6/8 bits = 8840 byte)
                                     (8840 - 36 (MAC header) - 34 (cipher) - 4 (FCS) - 36 (RDGBA) -4 (delimiter) = 8726)
    RESERVED14[15..14]           - (RO) Reserved bits
    AMSDU_MM_13M_TH[29..16]      - (RW) If Tx AMSDU, TXD's data length > AMSDU_MM_13M_TH, and the following conditions are met:
                                       BW20, mix mode, MCS32, force Tx rate to be MCS2.
                                       BW20, mix mode, MCS0, force Tx rate to be MCS2.
                                       BW20, VHT, Nss=1, MCS0, force Tx rate to be MCS2.
                                       BW40, mix mode, MCS32, force Tx rate to be MCS1.
                                       BW40, VHT, Nss=1, MCS0, force Tx rate to be MCS1.
                                       BW40, mix mode, MCS0, force Tx rate to be MCS1.
                                       BW20, VHT, Nss=2, MCS0, force Tx rate to be MCS1.
                                       BW20, mix mode, MCS8, force Tx rate to be MCS9.
                                       BW20, VHT, Nss-1, MCS1, force Tx rate to be MCS2.
                                       BW20, mix mode, MCS1, force Tx rate to be MCS2.
                                     (5440us (MAX_VHT_PSDU_DUR0~1)*13/8 bits = 4080 byte)
                                     (4080 - 36 (MAC header) - 34 (cipher) - 4 (FCS) - 36 (RDGBA) -4 (delimiter) = 3966)
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ARCR2_AMSDU_MM_13M_TH_ADDR              BN1_WF_AGG_TOP_ARCR2_ADDR
#define BN1_WF_AGG_TOP_ARCR2_AMSDU_MM_13M_TH_MASK              0x3FFF0000                // AMSDU_MM_13M_TH[29..16]
#define BN1_WF_AGG_TOP_ARCR2_AMSDU_MM_13M_TH_SHFT              16
#define BN1_WF_AGG_TOP_ARCR2_AMSDU_MM_6M_TH_ADDR               BN1_WF_AGG_TOP_ARCR2_ADDR
#define BN1_WF_AGG_TOP_ARCR2_AMSDU_MM_6M_TH_MASK               0x00003FFF                // AMSDU_MM_6M_TH[13..0]
#define BN1_WF_AGG_TOP_ARCR2_AMSDU_MM_6M_TH_SHFT               0

/* =====================================================================================

  ---ARUCR (0x820f2000 + 0x20)---

    RATE1_UP0_MPDU_LIMIT[2..0]   - (RW) Rate up TX count limit for Rate 1
                                     Select Rate 1 for the next PPDU if no rate down condition happens. Reset cumulated MPDU TX count and MPDU fail count if cumulated MPDU TX count reaches this limit and no rate down condition happens.
                                     3'h0: Limit 1
                                     3'h1: Limit 2
                                     ...
                                     3'h7: Limit 8
                                     (For DBDC channel 0)
    RESERVED3[3]                 - (RO) Reserved bits
    RATE2_UP0_MPDU_LIMIT[6..4]   - (RW) Rate 2 to Rate 1 up rate condition
                                     Same as RATE1_UP0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED7[7]                 - (RO) Reserved bits
    RATE3_UP0_MPDU_LIMIT[10..8]  - (RW) Rate 3 to Rate 2 up rate condition
                                     Same as RATE1_UP0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED11[11]               - (RO) Reserved bits
    RATE4_UP0_MPDU_LIMIT[14..12] - (RW) Rate 4 to Rate 2 up rate condition
                                     Same as RATE1_UP0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED15[15]               - (RO) Reserved bits
    RATE5_UP0_MPDU_LIMIT[18..16] - (RW) Rate 5 to Rate 4 up rate condition
                                     Same as RATE1_UP0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED19[19]               - (RO) Reserved bits
    RATE6_UP0_MPDU_LIMIT[22..20] - (RW) Rate 6 to Rate 4 up rate condition
                                     Same as RATE1_UP0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED23[23]               - (RO) Reserved bits
    RATE7_UP0_MPDU_LIMIT[26..24] - (RW) Rate 7 to Rate 4 up rate condition
                                     Same as RATE1_UP0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED27[27]               - (RO) Reserved bits
    RATE8_UP0_MPDU_LIMIT[30..28] - (RW) Rate 8 to Rate 4 up rate condition
                                     Same as RATE1_UP0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ARUCR_RATE8_UP0_MPDU_LIMIT_ADDR         BN1_WF_AGG_TOP_ARUCR_ADDR
#define BN1_WF_AGG_TOP_ARUCR_RATE8_UP0_MPDU_LIMIT_MASK         0x70000000                // RATE8_UP0_MPDU_LIMIT[30..28]
#define BN1_WF_AGG_TOP_ARUCR_RATE8_UP0_MPDU_LIMIT_SHFT         28
#define BN1_WF_AGG_TOP_ARUCR_RATE7_UP0_MPDU_LIMIT_ADDR         BN1_WF_AGG_TOP_ARUCR_ADDR
#define BN1_WF_AGG_TOP_ARUCR_RATE7_UP0_MPDU_LIMIT_MASK         0x07000000                // RATE7_UP0_MPDU_LIMIT[26..24]
#define BN1_WF_AGG_TOP_ARUCR_RATE7_UP0_MPDU_LIMIT_SHFT         24
#define BN1_WF_AGG_TOP_ARUCR_RATE6_UP0_MPDU_LIMIT_ADDR         BN1_WF_AGG_TOP_ARUCR_ADDR
#define BN1_WF_AGG_TOP_ARUCR_RATE6_UP0_MPDU_LIMIT_MASK         0x00700000                // RATE6_UP0_MPDU_LIMIT[22..20]
#define BN1_WF_AGG_TOP_ARUCR_RATE6_UP0_MPDU_LIMIT_SHFT         20
#define BN1_WF_AGG_TOP_ARUCR_RATE5_UP0_MPDU_LIMIT_ADDR         BN1_WF_AGG_TOP_ARUCR_ADDR
#define BN1_WF_AGG_TOP_ARUCR_RATE5_UP0_MPDU_LIMIT_MASK         0x00070000                // RATE5_UP0_MPDU_LIMIT[18..16]
#define BN1_WF_AGG_TOP_ARUCR_RATE5_UP0_MPDU_LIMIT_SHFT         16
#define BN1_WF_AGG_TOP_ARUCR_RATE4_UP0_MPDU_LIMIT_ADDR         BN1_WF_AGG_TOP_ARUCR_ADDR
#define BN1_WF_AGG_TOP_ARUCR_RATE4_UP0_MPDU_LIMIT_MASK         0x00007000                // RATE4_UP0_MPDU_LIMIT[14..12]
#define BN1_WF_AGG_TOP_ARUCR_RATE4_UP0_MPDU_LIMIT_SHFT         12
#define BN1_WF_AGG_TOP_ARUCR_RATE3_UP0_MPDU_LIMIT_ADDR         BN1_WF_AGG_TOP_ARUCR_ADDR
#define BN1_WF_AGG_TOP_ARUCR_RATE3_UP0_MPDU_LIMIT_MASK         0x00000700                // RATE3_UP0_MPDU_LIMIT[10..8]
#define BN1_WF_AGG_TOP_ARUCR_RATE3_UP0_MPDU_LIMIT_SHFT         8
#define BN1_WF_AGG_TOP_ARUCR_RATE2_UP0_MPDU_LIMIT_ADDR         BN1_WF_AGG_TOP_ARUCR_ADDR
#define BN1_WF_AGG_TOP_ARUCR_RATE2_UP0_MPDU_LIMIT_MASK         0x00000070                // RATE2_UP0_MPDU_LIMIT[6..4]
#define BN1_WF_AGG_TOP_ARUCR_RATE2_UP0_MPDU_LIMIT_SHFT         4
#define BN1_WF_AGG_TOP_ARUCR_RATE1_UP0_MPDU_LIMIT_ADDR         BN1_WF_AGG_TOP_ARUCR_ADDR
#define BN1_WF_AGG_TOP_ARUCR_RATE1_UP0_MPDU_LIMIT_MASK         0x00000007                // RATE1_UP0_MPDU_LIMIT[2..0]
#define BN1_WF_AGG_TOP_ARUCR_RATE1_UP0_MPDU_LIMIT_SHFT         0

/* =====================================================================================

  ---ARDCR (0x820f2000 + 0x24)---

    RATE1_DOWN0_MPDU_LIMIT[2..0] - (RW) Rate down fail count limit for Rate 1
                                     Select Rate 2 for the next PPDU once cumulated MPDU fail count reaches this limit and reset cumulated MPDU TX count and MPDU fail count.
                                     3'h0: Limit 1
                                     3'h1: Limit 2
                                     ...
                                     3'h7: Limit 8
                                     (For DBDC channel 0)
    RESERVED3[3]                 - (RO) Reserved bits
    RATE2_DOWN0_MPDU_LIMIT[6..4] - (RW) Rate 2 to Rate 3 down rate condition
                                     Same as RATE1_DOWN0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED7[7]                 - (RO) Reserved bits
    RATE3_DOWN0_MPDU_LIMIT[10..8] - (RW) Rate 3 to Rate 4 down rate condition
                                     Same as RATE1_DOWN0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED11[11]               - (RO) Reserved bits
    RATE4_DOWN0_MPDU_LIMIT[14..12] - (RW) Rate 4 to Rate 5 down rate condition
                                     Same as RATE1_DOWN0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED15[15]               - (RO) Reserved bits
    RATE5_DOWN0_MPDU_LIMIT[18..16] - (RW) Rate 5 to Rate 6 down rate condition
                                     Same as RATE1_DOWN0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED19[19]               - (RO) Reserved bits
    RATE6_DOWN0_MPDU_LIMIT[22..20] - (RW) Rate 6 to Rate 7 down rate condition
                                     Same as RATE1_DOWN0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED23[23]               - (RO) Reserved bits
    RATE7_DOWN0_MPDU_LIMIT[26..24] - (RW) Rate 7 to Rate 8 down rate condition
                                     Same as RATE1_DOWN0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED27[27]               - (RO) Reserved bits
    RATE8_DOWN0_MPDU_LIMIT[30..28] - (RW) Rate 8 to Rate 8 or Rate 1 down rate condition
                                     If RATE8_DOWN_CTL=0, down rate to Rate 8 for the next PPDU when the limit is reached.
                                     If RATE8_DOWN_CTL=1, down rate to Rate 1 for the next PPDU when the limit is reached.
                                     Same as RATE1_DOWN0_MDPU_LIMIT.
                                     (For DBDC channel 0)
    RESERVED31[31]               - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ARDCR_RATE8_DOWN0_MPDU_LIMIT_ADDR       BN1_WF_AGG_TOP_ARDCR_ADDR
#define BN1_WF_AGG_TOP_ARDCR_RATE8_DOWN0_MPDU_LIMIT_MASK       0x70000000                // RATE8_DOWN0_MPDU_LIMIT[30..28]
#define BN1_WF_AGG_TOP_ARDCR_RATE8_DOWN0_MPDU_LIMIT_SHFT       28
#define BN1_WF_AGG_TOP_ARDCR_RATE7_DOWN0_MPDU_LIMIT_ADDR       BN1_WF_AGG_TOP_ARDCR_ADDR
#define BN1_WF_AGG_TOP_ARDCR_RATE7_DOWN0_MPDU_LIMIT_MASK       0x07000000                // RATE7_DOWN0_MPDU_LIMIT[26..24]
#define BN1_WF_AGG_TOP_ARDCR_RATE7_DOWN0_MPDU_LIMIT_SHFT       24
#define BN1_WF_AGG_TOP_ARDCR_RATE6_DOWN0_MPDU_LIMIT_ADDR       BN1_WF_AGG_TOP_ARDCR_ADDR
#define BN1_WF_AGG_TOP_ARDCR_RATE6_DOWN0_MPDU_LIMIT_MASK       0x00700000                // RATE6_DOWN0_MPDU_LIMIT[22..20]
#define BN1_WF_AGG_TOP_ARDCR_RATE6_DOWN0_MPDU_LIMIT_SHFT       20
#define BN1_WF_AGG_TOP_ARDCR_RATE5_DOWN0_MPDU_LIMIT_ADDR       BN1_WF_AGG_TOP_ARDCR_ADDR
#define BN1_WF_AGG_TOP_ARDCR_RATE5_DOWN0_MPDU_LIMIT_MASK       0x00070000                // RATE5_DOWN0_MPDU_LIMIT[18..16]
#define BN1_WF_AGG_TOP_ARDCR_RATE5_DOWN0_MPDU_LIMIT_SHFT       16
#define BN1_WF_AGG_TOP_ARDCR_RATE4_DOWN0_MPDU_LIMIT_ADDR       BN1_WF_AGG_TOP_ARDCR_ADDR
#define BN1_WF_AGG_TOP_ARDCR_RATE4_DOWN0_MPDU_LIMIT_MASK       0x00007000                // RATE4_DOWN0_MPDU_LIMIT[14..12]
#define BN1_WF_AGG_TOP_ARDCR_RATE4_DOWN0_MPDU_LIMIT_SHFT       12
#define BN1_WF_AGG_TOP_ARDCR_RATE3_DOWN0_MPDU_LIMIT_ADDR       BN1_WF_AGG_TOP_ARDCR_ADDR
#define BN1_WF_AGG_TOP_ARDCR_RATE3_DOWN0_MPDU_LIMIT_MASK       0x00000700                // RATE3_DOWN0_MPDU_LIMIT[10..8]
#define BN1_WF_AGG_TOP_ARDCR_RATE3_DOWN0_MPDU_LIMIT_SHFT       8
#define BN1_WF_AGG_TOP_ARDCR_RATE2_DOWN0_MPDU_LIMIT_ADDR       BN1_WF_AGG_TOP_ARDCR_ADDR
#define BN1_WF_AGG_TOP_ARDCR_RATE2_DOWN0_MPDU_LIMIT_MASK       0x00000070                // RATE2_DOWN0_MPDU_LIMIT[6..4]
#define BN1_WF_AGG_TOP_ARDCR_RATE2_DOWN0_MPDU_LIMIT_SHFT       4
#define BN1_WF_AGG_TOP_ARDCR_RATE1_DOWN0_MPDU_LIMIT_ADDR       BN1_WF_AGG_TOP_ARDCR_ADDR
#define BN1_WF_AGG_TOP_ARDCR_RATE1_DOWN0_MPDU_LIMIT_MASK       0x00000007                // RATE1_DOWN0_MPDU_LIMIT[2..0]
#define BN1_WF_AGG_TOP_ARDCR_RATE1_DOWN0_MPDU_LIMIT_SHFT       0

/* =====================================================================================

  ---FRM1RR0 (0x820f2000 + 0x28)---

    D0_FRM1_RATE0[11..0]         - (RW) Rate to be Fixed:  (TXD_FR = 1'b1 and TXD_FRM = 1'b1)
                                     Fix rate mode 1 rate 0
                                     Bit[13]: STBC: indicate the transmission rate is STBC rate
                                     0: non-STBC
                                     1: STBC
                                     
                                     Bit[12:10]: Nsts: Indicate the count of space time stream
                                     3'b000: means Nsts = 1
                                     3'b001: means Nsts = 2
                                     3'b010: means Nsts = 3
                                     3'b011: means Nsts = 4
                                     3'b100: means Nsts = 5
                                     3'b101: means Nsts = 6
                                     3'b110: means Nsts = 7
                                     3'b111: means Nsts = 8
                                     
                                     In HT Case:
                                     Nss is determined by MCS
                                     Nsts and if STBC is enabled are determined by this field
                                     In VHT Case:
                                     If STBC field is 1. Nss = Nsts / 2
                                     If STBC field is 0. Nss = Nsts
                                     
                                     Bit[9:6]: TX Mode
                                     indicate the transmission mode
                                     4'b0000: Legacy CCK
                                     4'b0001: Legacy OFDM
                                     4'b0010: HT Mixed mode
                                     4'b0011: HT Green field mode
                                     4'b0100: VHT mode
                                     4'b0101~0111: reserved
                                     4'b1000: HE_SU
                                     4'b1001: HE_EXT_SU
                                     4'b1010: HE_TRIG
                                     4'b1011: HE_MU
                                     4'b1100~1111: reserved
                                     Bit[5:0]: TX rate
                                     For Legacy CCK:
                                     CCK: (long preamble)
                                     6'b00_0000: 1M
                                     6'b00_0001: 2M
                                     6'b00_0010: 5.5M
                                     6'b00_0011: 11M
                                     CCK: (short preamble)
                                     6'b00_0101: 2M
                                     6'b00_0110: 5.5M
                                     6'b00_0111: 11M
                                     
                                     For Legacy OFDM:
                                     6'b00_1011: 6M (in 20MHz channel spacing)
                                     6'b00_1111: 9M (in 20MHz channel spacing)
                                     6'b00_1010: 12M (in 20MHz channel spacing)
                                     6'b00_1110: 18M (in 20MHz channel spacing)
                                     6'b00_1001: 24M (in 20MHz channel spacing)
                                     6'b00_1101: 36M (in 20MHz channel spacing)
                                     6'b00_1000: 48M (in 20MHz channel spacing)
                                     6'b00_1100: 54M (in 20MHz channel spacing)
                                     
                                     For HT rate:
                                     The bits 0~5 indicate MCSN, N=0~23 and 32, others reserved
                                     
                                     For VHT rate:
                                     The bits 0~3 indicate MCSN, N=0~9, others reserved
                                     
                                     For HE rate:
                                     The bits 0~3 indicate MCSN, N=0~11, others reserved
                                     Under HE_ER_SU rate, the bit 45indicate RU106
                                     0: RU242
                                     1: RU106
                                     Under HE rate, the bit 4 indicate HE_DCM,
                                     0: non-DCM
                                     1: DCM
    RESERVED12[15..12]           - (RO) Reserved bits
    D0_FRM1_RATE1[27..16]        - (RW) Fix rate mode 1 rate 1
                                     HW will rate down to Rate 2 when packet fails.
                                     Same as D0_FRM1_RATE0.
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_FRM1RR0_D0_FRM1_RATE1_ADDR              BN1_WF_AGG_TOP_FRM1RR0_ADDR
#define BN1_WF_AGG_TOP_FRM1RR0_D0_FRM1_RATE1_MASK              0x0FFF0000                // D0_FRM1_RATE1[27..16]
#define BN1_WF_AGG_TOP_FRM1RR0_D0_FRM1_RATE1_SHFT              16
#define BN1_WF_AGG_TOP_FRM1RR0_D0_FRM1_RATE0_ADDR              BN1_WF_AGG_TOP_FRM1RR0_ADDR
#define BN1_WF_AGG_TOP_FRM1RR0_D0_FRM1_RATE0_MASK              0x00000FFF                // D0_FRM1_RATE0[11..0]
#define BN1_WF_AGG_TOP_FRM1RR0_D0_FRM1_RATE0_SHFT              0

/* =====================================================================================

  ---FRM1RR1 (0x820f2000 + 0x2c)---

    D0_FRM1_RATE2[11..0]         - (RW) Fix rate mode 1 rate 2
                                     HW will rate down to Rate 3 when packet fails.
                                     Same as D0_FRM1_RATE0.
    RESERVED12[15..12]           - (RO) Reserved bits
    D0_FRM1_RATE3[27..16]        - (RW) Fix rate mode 1 rate 3
                                     HW will rate down to Rate 4 when packet fails. 
                                     Same as D0_FRM1_RATE0.
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_FRM1RR1_D0_FRM1_RATE3_ADDR              BN1_WF_AGG_TOP_FRM1RR1_ADDR
#define BN1_WF_AGG_TOP_FRM1RR1_D0_FRM1_RATE3_MASK              0x0FFF0000                // D0_FRM1_RATE3[27..16]
#define BN1_WF_AGG_TOP_FRM1RR1_D0_FRM1_RATE3_SHFT              16
#define BN1_WF_AGG_TOP_FRM1RR1_D0_FRM1_RATE2_ADDR              BN1_WF_AGG_TOP_FRM1RR1_ADDR
#define BN1_WF_AGG_TOP_FRM1RR1_D0_FRM1_RATE2_MASK              0x00000FFF                // D0_FRM1_RATE2[11..0]
#define BN1_WF_AGG_TOP_FRM1RR1_D0_FRM1_RATE2_SHFT              0

/* =====================================================================================

  ---FRM1RR2 (0x820f2000 + 0x30)---

    D0_FRM1_RATE4[11..0]         - (RW) Fix rate mode 1 rate 4
                                     HW will rate down to Rate 5 when packet fails.
                                     Same as D0_FRM1_RATE0.
    RESERVED12[15..12]           - (RO) Reserved bits
    D0_FRM1_RATE5[27..16]        - (RW) Fix rate mode 1 rate 5
                                     HW will rate down to Rate 6 when packet fails. 
                                     Same as D0_FRM1_RATE0.
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_FRM1RR2_D0_FRM1_RATE5_ADDR              BN1_WF_AGG_TOP_FRM1RR2_ADDR
#define BN1_WF_AGG_TOP_FRM1RR2_D0_FRM1_RATE5_MASK              0x0FFF0000                // D0_FRM1_RATE5[27..16]
#define BN1_WF_AGG_TOP_FRM1RR2_D0_FRM1_RATE5_SHFT              16
#define BN1_WF_AGG_TOP_FRM1RR2_D0_FRM1_RATE4_ADDR              BN1_WF_AGG_TOP_FRM1RR2_ADDR
#define BN1_WF_AGG_TOP_FRM1RR2_D0_FRM1_RATE4_MASK              0x00000FFF                // D0_FRM1_RATE4[11..0]
#define BN1_WF_AGG_TOP_FRM1RR2_D0_FRM1_RATE4_SHFT              0

/* =====================================================================================

  ---FRM1RR3 (0x820f2000 + 0x34)---

    D0_FRM1_RATE6[11..0]         - (RW) Fix rate mode 1 rate 6
                                     HW will rate down to Rate7 when packet fails.
                                     Same as D0_FRM1_RATE0.
    RESERVED12[15..12]           - (RO) Reserved bits
    D0_FRM1_RATE7[27..16]        - (RW) Fix rate mode 1 rate 7
                                     HW will rate down to Rate 8 when packet fails. 
                                     Same as D0_FRM1_RATE0.
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_FRM1RR3_D0_FRM1_RATE7_ADDR              BN1_WF_AGG_TOP_FRM1RR3_ADDR
#define BN1_WF_AGG_TOP_FRM1RR3_D0_FRM1_RATE7_MASK              0x0FFF0000                // D0_FRM1_RATE7[27..16]
#define BN1_WF_AGG_TOP_FRM1RR3_D0_FRM1_RATE7_SHFT              16
#define BN1_WF_AGG_TOP_FRM1RR3_D0_FRM1_RATE6_ADDR              BN1_WF_AGG_TOP_FRM1RR3_ADDR
#define BN1_WF_AGG_TOP_FRM1RR3_D0_FRM1_RATE6_MASK              0x00000FFF                // D0_FRM1_RATE6[11..0]
#define BN1_WF_AGG_TOP_FRM1RR3_D0_FRM1_RATE6_SHFT              0

/* =====================================================================================

  ---FRM1RR4 (0x820f2000 + 0x38)---

    D0_FRM1_RATE8[11..0]         - (RW) Fix rate mode 1 rate 8
                                     HW will rate down to Rate 9 when packet fails.
                                     Same as D0_FRM1_RATE0.
    RESERVED12[15..12]           - (RO) Reserved bits
    D0_FRM1_RATE9[27..16]        - (RW) Fix rate mode 1 rate 9
                                     HW will rate down to Rate 10 when packet fails. 
                                     Same as D0_FRM1_RATE0.
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_FRM1RR4_D0_FRM1_RATE9_ADDR              BN1_WF_AGG_TOP_FRM1RR4_ADDR
#define BN1_WF_AGG_TOP_FRM1RR4_D0_FRM1_RATE9_MASK              0x0FFF0000                // D0_FRM1_RATE9[27..16]
#define BN1_WF_AGG_TOP_FRM1RR4_D0_FRM1_RATE9_SHFT              16
#define BN1_WF_AGG_TOP_FRM1RR4_D0_FRM1_RATE8_ADDR              BN1_WF_AGG_TOP_FRM1RR4_ADDR
#define BN1_WF_AGG_TOP_FRM1RR4_D0_FRM1_RATE8_MASK              0x00000FFF                // D0_FRM1_RATE8[11..0]
#define BN1_WF_AGG_TOP_FRM1RR4_D0_FRM1_RATE8_SHFT              0

/* =====================================================================================

  ---FRM1RR5 (0x820f2000 + 0x3c)---

    D0_FRM1_RATE10[11..0]        - (RW) Fix rate mode 1 rate 10
                                     HW will rate down to Rate 11 when packet fails.
                                     Same as D0_FRM1_RATE0.
    RESERVED12[15..12]           - (RO) Reserved bits
    D0_FRM1_RATE11[27..16]       - (RW) Fix rate mode 1 rate 11
                                     HW will rate down to Rate 12 when packet fails. 
                                     Same as D0_FRM1_RATE0.
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_FRM1RR5_D0_FRM1_RATE11_ADDR             BN1_WF_AGG_TOP_FRM1RR5_ADDR
#define BN1_WF_AGG_TOP_FRM1RR5_D0_FRM1_RATE11_MASK             0x0FFF0000                // D0_FRM1_RATE11[27..16]
#define BN1_WF_AGG_TOP_FRM1RR5_D0_FRM1_RATE11_SHFT             16
#define BN1_WF_AGG_TOP_FRM1RR5_D0_FRM1_RATE10_ADDR             BN1_WF_AGG_TOP_FRM1RR5_ADDR
#define BN1_WF_AGG_TOP_FRM1RR5_D0_FRM1_RATE10_MASK             0x00000FFF                // D0_FRM1_RATE10[11..0]
#define BN1_WF_AGG_TOP_FRM1RR5_D0_FRM1_RATE10_SHFT             0

/* =====================================================================================

  ---FRM1RR6 (0x820f2000 + 0x40)---

    D0_FRM1_RATE12[11..0]        - (RW) Fix rate mode 1 rate 12
                                     HW will rate down to Rate 13 when packet fails.
                                     Same as D0_FRM1_RATE0.
    RESERVED12[15..12]           - (RO) Reserved bits
    D0_FRM1_RATE13[27..16]       - (RW) Fix rate mode 1 rate 13
                                     HW will rate down to Rate 14 when packet fails. 
                                     Same as D0_FRM1_RATE0.
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_FRM1RR6_D0_FRM1_RATE13_ADDR             BN1_WF_AGG_TOP_FRM1RR6_ADDR
#define BN1_WF_AGG_TOP_FRM1RR6_D0_FRM1_RATE13_MASK             0x0FFF0000                // D0_FRM1_RATE13[27..16]
#define BN1_WF_AGG_TOP_FRM1RR6_D0_FRM1_RATE13_SHFT             16
#define BN1_WF_AGG_TOP_FRM1RR6_D0_FRM1_RATE12_ADDR             BN1_WF_AGG_TOP_FRM1RR6_ADDR
#define BN1_WF_AGG_TOP_FRM1RR6_D0_FRM1_RATE12_MASK             0x00000FFF                // D0_FRM1_RATE12[11..0]
#define BN1_WF_AGG_TOP_FRM1RR6_D0_FRM1_RATE12_SHFT             0

/* =====================================================================================

  ---FRM1RR7 (0x820f2000 + 0x44)---

    D0_FRM1_RATE14[11..0]        - (RW) Fix rate mode 1 rate 14
                                     HW will rate down to Rate 15 when packet fails.
                                     Same as D0_FRM1_RATE0.
    RESERVED12[15..12]           - (RO) Reserved bits
    D0_FRM1_RATE15[27..16]       - (RW) Fix rate mode 1 rate 15
                                     HW will finish Tx with ME in Tx status when packet fails. 
                                     Same as D0_FRM1_RATE0.
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_FRM1RR7_D0_FRM1_RATE15_ADDR             BN1_WF_AGG_TOP_FRM1RR7_ADDR
#define BN1_WF_AGG_TOP_FRM1RR7_D0_FRM1_RATE15_MASK             0x0FFF0000                // D0_FRM1_RATE15[27..16]
#define BN1_WF_AGG_TOP_FRM1RR7_D0_FRM1_RATE15_SHFT             16
#define BN1_WF_AGG_TOP_FRM1RR7_D0_FRM1_RATE14_ADDR             BN1_WF_AGG_TOP_FRM1RR7_ADDR
#define BN1_WF_AGG_TOP_FRM1RR7_D0_FRM1_RATE14_MASK             0x00000FFF                // D0_FRM1_RATE14[11..0]
#define BN1_WF_AGG_TOP_FRM1RR7_D0_FRM1_RATE14_SHFT             0

/* =====================================================================================

  ---AALCR0 (0x820f2000 + 0x48)---

    AC00_AGG_LIMIT[7..0]         - (RW) AC0 aggregation count limit
                                     This limits the MPDU numbers in an A-MPDU so that TXOP burst can be achieved. 
                                     6'd0: No limit (but hardware limitation is 256)
                                     6'd1~6'd255: Limited MPDU numbers in an A-MPDU
    AC01_AGG_LIMIT[15..8]        - (RW) Similar to AC0_AGG_LIMIT
    AC02_AGG_LIMIT[23..16]       - (RW) Similar to AC0_AGG_LIMIT
    AC03_AGG_LIMIT[31..24]       - (RW) Similar to AC0_AGG_LIMIT

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AALCR0_AC03_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR0_ADDR
#define BN1_WF_AGG_TOP_AALCR0_AC03_AGG_LIMIT_MASK              0xFF000000                // AC03_AGG_LIMIT[31..24]
#define BN1_WF_AGG_TOP_AALCR0_AC03_AGG_LIMIT_SHFT              24
#define BN1_WF_AGG_TOP_AALCR0_AC02_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR0_ADDR
#define BN1_WF_AGG_TOP_AALCR0_AC02_AGG_LIMIT_MASK              0x00FF0000                // AC02_AGG_LIMIT[23..16]
#define BN1_WF_AGG_TOP_AALCR0_AC02_AGG_LIMIT_SHFT              16
#define BN1_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR0_ADDR
#define BN1_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK              0x0000FF00                // AC01_AGG_LIMIT[15..8]
#define BN1_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT              8
#define BN1_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR0_ADDR
#define BN1_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK              0x000000FF                // AC00_AGG_LIMIT[7..0]
#define BN1_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT              0

/* =====================================================================================

  ---AALCR1 (0x820f2000 + 0x4c)---

    AC10_AGG_LIMIT[7..0]         - (RW) Similar to AC0_AGG_LIMIT
    AC11_AGG_LIMIT[15..8]        - (RW) Similar to AC0_AGG_LIMIT
    AC12_AGG_LIMIT[23..16]       - (RW) Similar to AC0_AGG_LIMIT
    AC13_AGG_LIMIT[31..24]       - (RW) Similar to AC0_AGG_LIMIT

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AALCR1_AC13_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR1_ADDR
#define BN1_WF_AGG_TOP_AALCR1_AC13_AGG_LIMIT_MASK              0xFF000000                // AC13_AGG_LIMIT[31..24]
#define BN1_WF_AGG_TOP_AALCR1_AC13_AGG_LIMIT_SHFT              24
#define BN1_WF_AGG_TOP_AALCR1_AC12_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR1_ADDR
#define BN1_WF_AGG_TOP_AALCR1_AC12_AGG_LIMIT_MASK              0x00FF0000                // AC12_AGG_LIMIT[23..16]
#define BN1_WF_AGG_TOP_AALCR1_AC12_AGG_LIMIT_SHFT              16
#define BN1_WF_AGG_TOP_AALCR1_AC11_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR1_ADDR
#define BN1_WF_AGG_TOP_AALCR1_AC11_AGG_LIMIT_MASK              0x0000FF00                // AC11_AGG_LIMIT[15..8]
#define BN1_WF_AGG_TOP_AALCR1_AC11_AGG_LIMIT_SHFT              8
#define BN1_WF_AGG_TOP_AALCR1_AC10_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR1_ADDR
#define BN1_WF_AGG_TOP_AALCR1_AC10_AGG_LIMIT_MASK              0x000000FF                // AC10_AGG_LIMIT[7..0]
#define BN1_WF_AGG_TOP_AALCR1_AC10_AGG_LIMIT_SHFT              0

/* =====================================================================================

  ---AALCR2 (0x820f2000 + 0x50)---

    AC20_AGG_LIMIT[7..0]         - (RW) Similar to AC0_AGG_LIMIT
    AC21_AGG_LIMIT[15..8]        - (RW) Similar to AC0_AGG_LIMIT
    AC22_AGG_LIMIT[23..16]       - (RW) Similar to AC0_AGG_LIMIT
    AC23_AGG_LIMIT[31..24]       - (RW) Similar to AC0_AGG_LIMIT

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AALCR2_AC23_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR2_ADDR
#define BN1_WF_AGG_TOP_AALCR2_AC23_AGG_LIMIT_MASK              0xFF000000                // AC23_AGG_LIMIT[31..24]
#define BN1_WF_AGG_TOP_AALCR2_AC23_AGG_LIMIT_SHFT              24
#define BN1_WF_AGG_TOP_AALCR2_AC22_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR2_ADDR
#define BN1_WF_AGG_TOP_AALCR2_AC22_AGG_LIMIT_MASK              0x00FF0000                // AC22_AGG_LIMIT[23..16]
#define BN1_WF_AGG_TOP_AALCR2_AC22_AGG_LIMIT_SHFT              16
#define BN1_WF_AGG_TOP_AALCR2_AC21_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR2_ADDR
#define BN1_WF_AGG_TOP_AALCR2_AC21_AGG_LIMIT_MASK              0x0000FF00                // AC21_AGG_LIMIT[15..8]
#define BN1_WF_AGG_TOP_AALCR2_AC21_AGG_LIMIT_SHFT              8
#define BN1_WF_AGG_TOP_AALCR2_AC20_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR2_ADDR
#define BN1_WF_AGG_TOP_AALCR2_AC20_AGG_LIMIT_MASK              0x000000FF                // AC20_AGG_LIMIT[7..0]
#define BN1_WF_AGG_TOP_AALCR2_AC20_AGG_LIMIT_SHFT              0

/* =====================================================================================

  ---AALCR3 (0x820f2000 + 0x54)---

    AC30_AGG_LIMIT[7..0]         - (RW) Similar to AC0_AGG_LIMIT
    AC31_AGG_LIMIT[15..8]        - (RW) Similar to AC0_AGG_LIMIT
    AC32_AGG_LIMIT[23..16]       - (RW) Similar to AC0_AGG_LIMIT
    AC33_AGG_LIMIT[31..24]       - (RW) Similar to AC0_AGG_LIMIT

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AALCR3_AC33_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR3_ADDR
#define BN1_WF_AGG_TOP_AALCR3_AC33_AGG_LIMIT_MASK              0xFF000000                // AC33_AGG_LIMIT[31..24]
#define BN1_WF_AGG_TOP_AALCR3_AC33_AGG_LIMIT_SHFT              24
#define BN1_WF_AGG_TOP_AALCR3_AC32_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR3_ADDR
#define BN1_WF_AGG_TOP_AALCR3_AC32_AGG_LIMIT_MASK              0x00FF0000                // AC32_AGG_LIMIT[23..16]
#define BN1_WF_AGG_TOP_AALCR3_AC32_AGG_LIMIT_SHFT              16
#define BN1_WF_AGG_TOP_AALCR3_AC31_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR3_ADDR
#define BN1_WF_AGG_TOP_AALCR3_AC31_AGG_LIMIT_MASK              0x0000FF00                // AC31_AGG_LIMIT[15..8]
#define BN1_WF_AGG_TOP_AALCR3_AC31_AGG_LIMIT_SHFT              8
#define BN1_WF_AGG_TOP_AALCR3_AC30_AGG_LIMIT_ADDR              BN1_WF_AGG_TOP_AALCR3_ADDR
#define BN1_WF_AGG_TOP_AALCR3_AC30_AGG_LIMIT_MASK              0x000000FF                // AC30_AGG_LIMIT[7..0]
#define BN1_WF_AGG_TOP_AALCR3_AC30_AGG_LIMIT_SHFT              0

/* =====================================================================================

  ---AALCR4 (0x820f2000 + 0x58)---

    ALTX0_AGG_LIMIT[7..0]        - (RW) Similar to AC0_AGG_LIMIT
    RESERVED8[31..8]             - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AALCR4_ALTX0_AGG_LIMIT_ADDR             BN1_WF_AGG_TOP_AALCR4_ADDR
#define BN1_WF_AGG_TOP_AALCR4_ALTX0_AGG_LIMIT_MASK             0x000000FF                // ALTX0_AGG_LIMIT[7..0]
#define BN1_WF_AGG_TOP_AALCR4_ALTX0_AGG_LIMIT_SHFT             0

/* =====================================================================================

  ---AWSCR0 (0x820f2000 + 0x5c)---

    WINSIZE0[7..0]               - (RW) AMPDU window size limit 0
                                     This limits the SN window size in an A-MPDU so that TXOP burst can be achieved. 
                                     6'd0: No limit (but hardware limitation is 256)
                                     6'd1~6'd255: Limited SN window size in an A-MPDU
    WINSIZE1[15..8]              - (RW) Similar to WINSIZE0
    WINSIZE2[23..16]             - (RW) Similar to WINSIZE0
    WINSIZE3[31..24]             - (RW) Similar to WINSIZE0

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AWSCR0_WINSIZE3_ADDR                    BN1_WF_AGG_TOP_AWSCR0_ADDR
#define BN1_WF_AGG_TOP_AWSCR0_WINSIZE3_MASK                    0xFF000000                // WINSIZE3[31..24]
#define BN1_WF_AGG_TOP_AWSCR0_WINSIZE3_SHFT                    24
#define BN1_WF_AGG_TOP_AWSCR0_WINSIZE2_ADDR                    BN1_WF_AGG_TOP_AWSCR0_ADDR
#define BN1_WF_AGG_TOP_AWSCR0_WINSIZE2_MASK                    0x00FF0000                // WINSIZE2[23..16]
#define BN1_WF_AGG_TOP_AWSCR0_WINSIZE2_SHFT                    16
#define BN1_WF_AGG_TOP_AWSCR0_WINSIZE1_ADDR                    BN1_WF_AGG_TOP_AWSCR0_ADDR
#define BN1_WF_AGG_TOP_AWSCR0_WINSIZE1_MASK                    0x0000FF00                // WINSIZE1[15..8]
#define BN1_WF_AGG_TOP_AWSCR0_WINSIZE1_SHFT                    8
#define BN1_WF_AGG_TOP_AWSCR0_WINSIZE0_ADDR                    BN1_WF_AGG_TOP_AWSCR0_ADDR
#define BN1_WF_AGG_TOP_AWSCR0_WINSIZE0_MASK                    0x000000FF                // WINSIZE0[7..0]
#define BN1_WF_AGG_TOP_AWSCR0_WINSIZE0_SHFT                    0

/* =====================================================================================

  ---AWSCR1 (0x820f2000 + 0x60)---

    WINSIZE4[7..0]               - (RW) Similar to WINSIZE0
    WINSIZE5[15..8]              - (RW) Similar to WINSIZE0
    WINSIZE6[23..16]             - (RW) Similar to WINSIZE0
    WINSIZE7[31..24]             - (RW) Similar to WINSIZE0

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AWSCR1_WINSIZE7_ADDR                    BN1_WF_AGG_TOP_AWSCR1_ADDR
#define BN1_WF_AGG_TOP_AWSCR1_WINSIZE7_MASK                    0xFF000000                // WINSIZE7[31..24]
#define BN1_WF_AGG_TOP_AWSCR1_WINSIZE7_SHFT                    24
#define BN1_WF_AGG_TOP_AWSCR1_WINSIZE6_ADDR                    BN1_WF_AGG_TOP_AWSCR1_ADDR
#define BN1_WF_AGG_TOP_AWSCR1_WINSIZE6_MASK                    0x00FF0000                // WINSIZE6[23..16]
#define BN1_WF_AGG_TOP_AWSCR1_WINSIZE6_SHFT                    16
#define BN1_WF_AGG_TOP_AWSCR1_WINSIZE5_ADDR                    BN1_WF_AGG_TOP_AWSCR1_ADDR
#define BN1_WF_AGG_TOP_AWSCR1_WINSIZE5_MASK                    0x0000FF00                // WINSIZE5[15..8]
#define BN1_WF_AGG_TOP_AWSCR1_WINSIZE5_SHFT                    8
#define BN1_WF_AGG_TOP_AWSCR1_WINSIZE4_ADDR                    BN1_WF_AGG_TOP_AWSCR1_ADDR
#define BN1_WF_AGG_TOP_AWSCR1_WINSIZE4_MASK                    0x000000FF                // WINSIZE4[7..0]
#define BN1_WF_AGG_TOP_AWSCR1_WINSIZE4_SHFT                    0

/* =====================================================================================

  ---AWSCR2 (0x820f2000 + 0x64)---

    WINSIZE8[7..0]               - (RW) Similar to WINSIZE0
    WINSIZE9[15..8]              - (RW) Similar to WINSIZE0
    WINSIZEA[23..16]             - (RW) Similar to WINSIZE0
    WINSIZEB[31..24]             - (RW) Similar to WINSIZE0

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AWSCR2_WINSIZEB_ADDR                    BN1_WF_AGG_TOP_AWSCR2_ADDR
#define BN1_WF_AGG_TOP_AWSCR2_WINSIZEB_MASK                    0xFF000000                // WINSIZEB[31..24]
#define BN1_WF_AGG_TOP_AWSCR2_WINSIZEB_SHFT                    24
#define BN1_WF_AGG_TOP_AWSCR2_WINSIZEA_ADDR                    BN1_WF_AGG_TOP_AWSCR2_ADDR
#define BN1_WF_AGG_TOP_AWSCR2_WINSIZEA_MASK                    0x00FF0000                // WINSIZEA[23..16]
#define BN1_WF_AGG_TOP_AWSCR2_WINSIZEA_SHFT                    16
#define BN1_WF_AGG_TOP_AWSCR2_WINSIZE9_ADDR                    BN1_WF_AGG_TOP_AWSCR2_ADDR
#define BN1_WF_AGG_TOP_AWSCR2_WINSIZE9_MASK                    0x0000FF00                // WINSIZE9[15..8]
#define BN1_WF_AGG_TOP_AWSCR2_WINSIZE9_SHFT                    8
#define BN1_WF_AGG_TOP_AWSCR2_WINSIZE8_ADDR                    BN1_WF_AGG_TOP_AWSCR2_ADDR
#define BN1_WF_AGG_TOP_AWSCR2_WINSIZE8_MASK                    0x000000FF                // WINSIZE8[7..0]
#define BN1_WF_AGG_TOP_AWSCR2_WINSIZE8_SHFT                    0

/* =====================================================================================

  ---AWSCR3 (0x820f2000 + 0x68)---

    WINSIZEC[7..0]               - (RW) Similar to WINSIZE0
    WINSIZED[15..8]              - (RW) Similar to WINSIZE0
    WINSIZEE[23..16]             - (RW) Similar to WINSIZE0
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AWSCR3_WINSIZEE_ADDR                    BN1_WF_AGG_TOP_AWSCR3_ADDR
#define BN1_WF_AGG_TOP_AWSCR3_WINSIZEE_MASK                    0x00FF0000                // WINSIZEE[23..16]
#define BN1_WF_AGG_TOP_AWSCR3_WINSIZEE_SHFT                    16
#define BN1_WF_AGG_TOP_AWSCR3_WINSIZED_ADDR                    BN1_WF_AGG_TOP_AWSCR3_ADDR
#define BN1_WF_AGG_TOP_AWSCR3_WINSIZED_MASK                    0x0000FF00                // WINSIZED[15..8]
#define BN1_WF_AGG_TOP_AWSCR3_WINSIZED_SHFT                    8
#define BN1_WF_AGG_TOP_AWSCR3_WINSIZEC_ADDR                    BN1_WF_AGG_TOP_AWSCR3_ADDR
#define BN1_WF_AGG_TOP_AWSCR3_WINSIZEC_MASK                    0x000000FF                // WINSIZEC[7..0]
#define BN1_WF_AGG_TOP_AWSCR3_WINSIZEC_SHFT                    0

/* =====================================================================================

  ---PCR0 (0x820f2000 + 0x6c)---

    MM_PROTECTION0[0]            - (RW) Controls protection mechanism for transmitting mixed mode packet
                                     Using RTS/CTS or CTS2 self protection is controlled by RTS_Threshold.
                                     1'b0: Use protection depending on other protection settings
                                     1'b1: Use protection
    GF_PROTECTION0[1]            - (RW) Controls protection mechanism for transmitting green field packet
                                     Using RTS/CTS or CTS2 self protection is controlled by RTS_Threshold.
                                     1'b0: Use protection depending on other protection settings
                                     1'b1: Use protection
    BW20_PROTECTION0[2]          - (RW) Protection mechanism when under 20MHz bandwidth
                                     1'b0: Use protection depending on other protection settings
                                     1'b1: Apply protection mechanism before transmitting frames when under 40MHz bandwidth
    PROTECTION_MODE0[3]          - (RW) Enables data frame protection
                                     1'b0: Long NAV Protect 
                                     1'b1: Short NAV Protect
                                     Note: When TX_RIFS_EN of RCR is enabled, this bit will be useless. HW will switch to Long-NAV protection mode.
    BW40_PROTECTION0[4]          - (RW) Protection mechanism when under 40MHz bandwidth
                                     1'b0: Use protection depending on other protection settings
                                     1'b1: Apply protection mechanism before transmitting frames when under 40MHz bandwidth
    RIFS_PROTECTION0[5]          - (RW) Controls protection mechanism for transmitting unicast frame with ACK policy set to No ACK and TX_RIFS_EN enabled
                                     If the frame length is shorter than RTS_Threshold, a CTS2Self protection mechanism will be applied; otherwise RTS/CTS will be used.
                                     1'b0. Use protection depending on other protection settings
                                     1'b1. Use protection
    BW80_PROTECTION0[6]          - (RW) Protection mechanism when under 80MHz bandwidth
                                     1'b1: Apply protection mechanism before transmitting frames when under 80MHz bandwidth
                                     1'b0: Use protection depending on other protection settings
    BW160_PROTECTION0[7]         - (RW) Protection mechanism when under 160MHz bandwidth
                                     1'b0: Use protection depending on other protection settings
                                     1'b1: Apply protection mechanism before transmitting frames when under 160MHz bandwidth
    ERP_PROTECTION0[12..8]       - (RW) When set, send a CTS frame before the OFDM frame if the OFDM frame length is shorter than RTS_threshold. If the OFDM frame length is longer than RTS_threshold, a CCK RTS will be transmitted before this OFDM frame. Used in 802.11g to quite the legacy station.
                                     [0]: For OM0, 11~3f 
                                     [1]: For OM1(Apply to both Band0 and Band1)
                                     [2]: For OM2(Apply to both Band0 and Band1)
                                     [3]: For OM3(Apply to both Band0 and Band1)
                                     [4]: For OM4(Apply to both Band0 and Band1)
    VHT_PROTECTION0[13]          - (RW) Controls protection mechanism for transmitting VHT mode packet
                                     Using RTS/CTS or CTS2 self protection is controlled by RTS_Threshold.
                                     1'b0: Use protection depending on other protection settings
                                     1'b1: Use protection
    TXOP_MODE0[14]               - (RW) TXOP mode
                                     0: 1st PPDU's aggregation has no TXOP limation (even TXOP=0). The following PPDU and its response don't violate remain TXOP
                                     1: 1st PPDU's aggregation has no TXOP limation (even TXOP=0). The following PPDU and its response still has no TXOP limation if the initial check of this PPDU's remain_TXOP>0. The following PPDU don't Tx if the initial check of this PPDU's remain_TXOP=0.
    PROTECTION_DIS_IN_PTA_WIN0[15] - (RW) 0: Allow protection frame in PTA window
                                     1: Disable protection frame in PTA window
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_PCR0_PROTECTION_DIS_IN_PTA_WIN0_ADDR    BN1_WF_AGG_TOP_PCR0_ADDR
#define BN1_WF_AGG_TOP_PCR0_PROTECTION_DIS_IN_PTA_WIN0_MASK    0x00008000                // PROTECTION_DIS_IN_PTA_WIN0[15]
#define BN1_WF_AGG_TOP_PCR0_PROTECTION_DIS_IN_PTA_WIN0_SHFT    15
#define BN1_WF_AGG_TOP_PCR0_TXOP_MODE0_ADDR                    BN1_WF_AGG_TOP_PCR0_ADDR
#define BN1_WF_AGG_TOP_PCR0_TXOP_MODE0_MASK                    0x00004000                // TXOP_MODE0[14]
#define BN1_WF_AGG_TOP_PCR0_TXOP_MODE0_SHFT                    14
#define BN1_WF_AGG_TOP_PCR0_VHT_PROTECTION0_ADDR               BN1_WF_AGG_TOP_PCR0_ADDR
#define BN1_WF_AGG_TOP_PCR0_VHT_PROTECTION0_MASK               0x00002000                // VHT_PROTECTION0[13]
#define BN1_WF_AGG_TOP_PCR0_VHT_PROTECTION0_SHFT               13
#define BN1_WF_AGG_TOP_PCR0_ERP_PROTECTION0_ADDR               BN1_WF_AGG_TOP_PCR0_ADDR
#define BN1_WF_AGG_TOP_PCR0_ERP_PROTECTION0_MASK               0x00001F00                // ERP_PROTECTION0[12..8]
#define BN1_WF_AGG_TOP_PCR0_ERP_PROTECTION0_SHFT               8
#define BN1_WF_AGG_TOP_PCR0_BW160_PROTECTION0_ADDR             BN1_WF_AGG_TOP_PCR0_ADDR
#define BN1_WF_AGG_TOP_PCR0_BW160_PROTECTION0_MASK             0x00000080                // BW160_PROTECTION0[7]
#define BN1_WF_AGG_TOP_PCR0_BW160_PROTECTION0_SHFT             7
#define BN1_WF_AGG_TOP_PCR0_BW80_PROTECTION0_ADDR              BN1_WF_AGG_TOP_PCR0_ADDR
#define BN1_WF_AGG_TOP_PCR0_BW80_PROTECTION0_MASK              0x00000040                // BW80_PROTECTION0[6]
#define BN1_WF_AGG_TOP_PCR0_BW80_PROTECTION0_SHFT              6
#define BN1_WF_AGG_TOP_PCR0_RIFS_PROTECTION0_ADDR              BN1_WF_AGG_TOP_PCR0_ADDR
#define BN1_WF_AGG_TOP_PCR0_RIFS_PROTECTION0_MASK              0x00000020                // RIFS_PROTECTION0[5]
#define BN1_WF_AGG_TOP_PCR0_RIFS_PROTECTION0_SHFT              5
#define BN1_WF_AGG_TOP_PCR0_BW40_PROTECTION0_ADDR              BN1_WF_AGG_TOP_PCR0_ADDR
#define BN1_WF_AGG_TOP_PCR0_BW40_PROTECTION0_MASK              0x00000010                // BW40_PROTECTION0[4]
#define BN1_WF_AGG_TOP_PCR0_BW40_PROTECTION0_SHFT              4
#define BN1_WF_AGG_TOP_PCR0_PROTECTION_MODE0_ADDR              BN1_WF_AGG_TOP_PCR0_ADDR
#define BN1_WF_AGG_TOP_PCR0_PROTECTION_MODE0_MASK              0x00000008                // PROTECTION_MODE0[3]
#define BN1_WF_AGG_TOP_PCR0_PROTECTION_MODE0_SHFT              3
#define BN1_WF_AGG_TOP_PCR0_BW20_PROTECTION0_ADDR              BN1_WF_AGG_TOP_PCR0_ADDR
#define BN1_WF_AGG_TOP_PCR0_BW20_PROTECTION0_MASK              0x00000004                // BW20_PROTECTION0[2]
#define BN1_WF_AGG_TOP_PCR0_BW20_PROTECTION0_SHFT              2
#define BN1_WF_AGG_TOP_PCR0_GF_PROTECTION0_ADDR                BN1_WF_AGG_TOP_PCR0_ADDR
#define BN1_WF_AGG_TOP_PCR0_GF_PROTECTION0_MASK                0x00000002                // GF_PROTECTION0[1]
#define BN1_WF_AGG_TOP_PCR0_GF_PROTECTION0_SHFT                1
#define BN1_WF_AGG_TOP_PCR0_MM_PROTECTION0_ADDR                BN1_WF_AGG_TOP_PCR0_ADDR
#define BN1_WF_AGG_TOP_PCR0_MM_PROTECTION0_MASK                0x00000001                // MM_PROTECTION0[0]
#define BN1_WF_AGG_TOP_PCR0_MM_PROTECTION0_SHFT                0

/* =====================================================================================

  ---PCR1 (0x820f2000 + 0x70)---

    RTS0_PKT_LEN_THRESHOLD[19..0] - (RW) If the packet length is longer than or equal to the threshold valuen and it is a UC, the RTS/CTS frame will be required.
    RESERVED20[22..20]           - (RO) Reserved bits
    RTS0_PKT_NUM_THRESHOLD[31..23] - (RW) If the packet number is bigger than or equal to the threshold valuen and it is a UC, the RTS/CTS frame will be required.
                                     7'd0: 1 packet
                                     7'd1: 2 packets
                                     ...
                                     7'd255: 256 packets
                                     7'd257~7'd511: Disable this function (do not use RTS/CTS for packet number)

 =====================================================================================*/
#define BN1_WF_AGG_TOP_PCR1_RTS0_PKT_NUM_THRESHOLD_ADDR        BN1_WF_AGG_TOP_PCR1_ADDR
#define BN1_WF_AGG_TOP_PCR1_RTS0_PKT_NUM_THRESHOLD_MASK        0xFF800000                // RTS0_PKT_NUM_THRESHOLD[31..23]
#define BN1_WF_AGG_TOP_PCR1_RTS0_PKT_NUM_THRESHOLD_SHFT        23
#define BN1_WF_AGG_TOP_PCR1_RTS0_PKT_LEN_THRESHOLD_ADDR        BN1_WF_AGG_TOP_PCR1_ADDR
#define BN1_WF_AGG_TOP_PCR1_RTS0_PKT_LEN_THRESHOLD_MASK        0x000FFFFF                // RTS0_PKT_LEN_THRESHOLD[19..0]
#define BN1_WF_AGG_TOP_PCR1_RTS0_PKT_LEN_THRESHOLD_SHFT        0

/* =====================================================================================

  ---PCR3 (0x820f2000 + 0x74)---

    BN0_PTEC_FIX_RATE[9..0]      - (RW) Protection fixed rate for all BSSID (RTS/CTS2Sslf)
                                     Bit[8:6]: TX mode
                                     Indicates the transmission mode
                                     3'b000: Legacy CCK
                                     3'b001: Legacy OFDM
                                     3'bothers: Reserved
                                     Bit[5:0]: TX rate
                                     For Legacy CCK:
                                     CCK long preamble:
                                     6'b00_0000: 1M
                                     6'b00_0001: 2M
                                     6'b00_0010: 5.5M
                                     6'b00_0011: 11M
                                     CCK short preamble:
                                     6'b00_0101: 2M
                                     6'b00_0110: 5.5M
                                     6'b00_0111: 11M
                                     For Legacy OFDM:
                                     6'b00_1011: 6M
                                     6'b00_1111: 9M
                                     6'b00_1010: 12M
                                     6'b00_1110: 18M
                                     6'b00_1001: 24M
                                     6'b00_1101: 36M
                                     6'b00_1000: 48M
                                     6'b00_1100: 54M
    BN0_PTEC_RATE_SEL[10]        - (RW) Selects protection rate for all BSSID
                                     1'b0: Select fixed protection rate
                                     1'b1: Select auto protection rate
    BN0_PTEC_ER_EN[11]           - (RW) Allow to use HE Extended Range PPDU Rate for Protection Packet
                                     0: Not allow
                                     1: if following TX packet is HE ER SU, use the same TX rate for protection packet
    BN0_PTEC_HELTF_TYPE[13..12]  - (RW) Indicate HE LTF Type for HE protection TX packet(non HE use 2'b0)
    BN0_PTEC_HEGI_TYPE[15..14]   - (RW) Indicate HE GI Type for HE protection TX packet(non HE use 2'b0)
    BN0_PTEC_SPE_IDX[20..16]     - (RW) Spatial expansion table index for all BSSID
    RESERVED21[23..21]           - (RO) Reserved bits
    BN0_PTEC_SPE_SEL[24]         - (RW) Protection SPE_IDX mode for all BSSID
                                     1'b0: Select BN0_PCR.PTEC_SPE_IDX setting
                                     1'b1: Follow the  frame's SPE_IDX
    BN0_PTEC_HE_PE[26..25]       - (RW) (Packet Extension), Maximum PE capabilities defined in HE Capabilities field, which are factors of NSS, RU and Constellation Index:
                                     0 : 0us, TPE: 0us (no Packet Extension)
                                     1 : 8us, TPE:  0us, 4us, 8us
                                     2 : 16us, TPE:  4us, 8us, 12us and 16us
                                     3 : reserved
    RESERVED27[30..27]           - (RO) Reserved bits
    BN0_PTEC_ERP_RATE_SEL[31]    - (RW) ERP Protection rate select
                                     1'b0: Select CCK long preamble rate 
                                     1'b1: Select CCK short preamble rate

 =====================================================================================*/
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_ERP_RATE_SEL_ADDR         BN1_WF_AGG_TOP_PCR3_ADDR
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_ERP_RATE_SEL_MASK         0x80000000                // BN0_PTEC_ERP_RATE_SEL[31]
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_ERP_RATE_SEL_SHFT         31
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_HE_PE_ADDR                BN1_WF_AGG_TOP_PCR3_ADDR
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_HE_PE_MASK                0x06000000                // BN0_PTEC_HE_PE[26..25]
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_HE_PE_SHFT                25
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_SPE_SEL_ADDR              BN1_WF_AGG_TOP_PCR3_ADDR
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_SPE_SEL_MASK              0x01000000                // BN0_PTEC_SPE_SEL[24]
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_SPE_SEL_SHFT              24
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_SPE_IDX_ADDR              BN1_WF_AGG_TOP_PCR3_ADDR
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_SPE_IDX_MASK              0x001F0000                // BN0_PTEC_SPE_IDX[20..16]
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_SPE_IDX_SHFT              16
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_HEGI_TYPE_ADDR            BN1_WF_AGG_TOP_PCR3_ADDR
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_HEGI_TYPE_MASK            0x0000C000                // BN0_PTEC_HEGI_TYPE[15..14]
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_HEGI_TYPE_SHFT            14
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_HELTF_TYPE_ADDR           BN1_WF_AGG_TOP_PCR3_ADDR
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_HELTF_TYPE_MASK           0x00003000                // BN0_PTEC_HELTF_TYPE[13..12]
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_HELTF_TYPE_SHFT           12
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_ER_EN_ADDR                BN1_WF_AGG_TOP_PCR3_ADDR
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_ER_EN_MASK                0x00000800                // BN0_PTEC_ER_EN[11]
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_ER_EN_SHFT                11
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_RATE_SEL_ADDR             BN1_WF_AGG_TOP_PCR3_ADDR
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_RATE_SEL_MASK             0x00000400                // BN0_PTEC_RATE_SEL[10]
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_RATE_SEL_SHFT             10
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_FIX_RATE_ADDR             BN1_WF_AGG_TOP_PCR3_ADDR
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_FIX_RATE_MASK             0x000003FF                // BN0_PTEC_FIX_RATE[9..0]
#define BN1_WF_AGG_TOP_PCR3_BN0_PTEC_FIX_RATE_SHFT             0

/* =====================================================================================

  ---PCR4 (0x820f2000 + 0x78)---

    BN0_PTEC_ANT_ID[23..0]       - (RW) Global ANT_ID setting for protection frame
    RESERVED24[30..24]           - (RO) Reserved bits
    BN0_PTEC_ANT_ID_SEL[31]      - (RW) Protection ANT_ID mode for all BSSID
                                     1'b0: Select global ANT_ID setting
                                     1'b1: Follow the TX frame's ANT_ID

 =====================================================================================*/
#define BN1_WF_AGG_TOP_PCR4_BN0_PTEC_ANT_ID_SEL_ADDR           BN1_WF_AGG_TOP_PCR4_ADDR
#define BN1_WF_AGG_TOP_PCR4_BN0_PTEC_ANT_ID_SEL_MASK           0x80000000                // BN0_PTEC_ANT_ID_SEL[31]
#define BN1_WF_AGG_TOP_PCR4_BN0_PTEC_ANT_ID_SEL_SHFT           31
#define BN1_WF_AGG_TOP_PCR4_BN0_PTEC_ANT_ID_ADDR               BN1_WF_AGG_TOP_PCR4_ADDR
#define BN1_WF_AGG_TOP_PCR4_BN0_PTEC_ANT_ID_MASK               0x00FFFFFF                // BN0_PTEC_ANT_ID[23..0]
#define BN1_WF_AGG_TOP_PCR4_BN0_PTEC_ANT_ID_SHFT               0

/* =====================================================================================

  ---TTCR0 (0x820f2000 + 0x7c)---

    DYNAMIC_TXOP_TRUNCATION[0]   - (RW) Dynamic TXOP truncation Enable. 
                                     0:Disable
                                     1:Enable
    TXOP_TRUNC_UNDER_PRIMARY_USER_CHANGE[1] - (RW) Dynamic TXOP truncation Enable if primary user changes. 
                                     0: Not Do txop truncation check when primary user changes
                                     1: Do txop truncation check when primary user changes
    RESERVED2[7..2]              - (RO) Reserved bits
    DYN_TXOP_TRUNC_MPDU_TH_0[15..8] - (RW) Dynamic TXOP truncation MPDU number Threshold for TX Bit Rate <= 97.5Mbps
    DYN_TXOP_TRUNC_MPDU_TH_1[23..16] - (RW) Dynamic TXOP truncation MPDU number Threshold for 97.5Mbps < TX Bit Rate <= 195Mbps
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TTCR0_DYN_TXOP_TRUNC_MPDU_TH_1_ADDR     BN1_WF_AGG_TOP_TTCR0_ADDR
#define BN1_WF_AGG_TOP_TTCR0_DYN_TXOP_TRUNC_MPDU_TH_1_MASK     0x00FF0000                // DYN_TXOP_TRUNC_MPDU_TH_1[23..16]
#define BN1_WF_AGG_TOP_TTCR0_DYN_TXOP_TRUNC_MPDU_TH_1_SHFT     16
#define BN1_WF_AGG_TOP_TTCR0_DYN_TXOP_TRUNC_MPDU_TH_0_ADDR     BN1_WF_AGG_TOP_TTCR0_ADDR
#define BN1_WF_AGG_TOP_TTCR0_DYN_TXOP_TRUNC_MPDU_TH_0_MASK     0x0000FF00                // DYN_TXOP_TRUNC_MPDU_TH_0[15..8]
#define BN1_WF_AGG_TOP_TTCR0_DYN_TXOP_TRUNC_MPDU_TH_0_SHFT     8
#define BN1_WF_AGG_TOP_TTCR0_TXOP_TRUNC_UNDER_PRIMARY_USER_CHANGE_ADDR BN1_WF_AGG_TOP_TTCR0_ADDR
#define BN1_WF_AGG_TOP_TTCR0_TXOP_TRUNC_UNDER_PRIMARY_USER_CHANGE_MASK 0x00000002                // TXOP_TRUNC_UNDER_PRIMARY_USER_CHANGE[1]
#define BN1_WF_AGG_TOP_TTCR0_TXOP_TRUNC_UNDER_PRIMARY_USER_CHANGE_SHFT 1
#define BN1_WF_AGG_TOP_TTCR0_DYNAMIC_TXOP_TRUNCATION_ADDR      BN1_WF_AGG_TOP_TTCR0_ADDR
#define BN1_WF_AGG_TOP_TTCR0_DYNAMIC_TXOP_TRUNCATION_MASK      0x00000001                // DYNAMIC_TXOP_TRUNCATION[0]
#define BN1_WF_AGG_TOP_TTCR0_DYNAMIC_TXOP_TRUNCATION_SHFT      0

/* =====================================================================================

  ---TTCR1 (0x820f2000 + 0x80)---

    DYN_TXOP_TRUNC_MPDU_TH_3[7..0] - (RW) Dynamic TXOP truncation MPDU number Threshold for 325Mbps < TX Bit Rate <= 433Mbps
    DYN_TXOP_TRUNC_MPDU_TH_4[15..8] - (RW) Dynamic TXOP truncation MPDU number Threshold for 433Mbps < TX Bit Rate <= 866.7Mbps
    DYN_TXOP_TRUNC_MPDU_TH_5[23..16] - (RW) Dynamic TXOP truncation MPDU number Threshold for 866.7Mbps < TX Bit Rate <= 1300Mbps
    DYN_TXOP_TRUNC_MPDU_TH_6[31..24] - (RW) Dynamic TXOP truncation MPDU number Threshold for 1300 Mbps <  TX Bit Rate

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TTCR1_DYN_TXOP_TRUNC_MPDU_TH_6_ADDR     BN1_WF_AGG_TOP_TTCR1_ADDR
#define BN1_WF_AGG_TOP_TTCR1_DYN_TXOP_TRUNC_MPDU_TH_6_MASK     0xFF000000                // DYN_TXOP_TRUNC_MPDU_TH_6[31..24]
#define BN1_WF_AGG_TOP_TTCR1_DYN_TXOP_TRUNC_MPDU_TH_6_SHFT     24
#define BN1_WF_AGG_TOP_TTCR1_DYN_TXOP_TRUNC_MPDU_TH_5_ADDR     BN1_WF_AGG_TOP_TTCR1_ADDR
#define BN1_WF_AGG_TOP_TTCR1_DYN_TXOP_TRUNC_MPDU_TH_5_MASK     0x00FF0000                // DYN_TXOP_TRUNC_MPDU_TH_5[23..16]
#define BN1_WF_AGG_TOP_TTCR1_DYN_TXOP_TRUNC_MPDU_TH_5_SHFT     16
#define BN1_WF_AGG_TOP_TTCR1_DYN_TXOP_TRUNC_MPDU_TH_4_ADDR     BN1_WF_AGG_TOP_TTCR1_ADDR
#define BN1_WF_AGG_TOP_TTCR1_DYN_TXOP_TRUNC_MPDU_TH_4_MASK     0x0000FF00                // DYN_TXOP_TRUNC_MPDU_TH_4[15..8]
#define BN1_WF_AGG_TOP_TTCR1_DYN_TXOP_TRUNC_MPDU_TH_4_SHFT     8
#define BN1_WF_AGG_TOP_TTCR1_DYN_TXOP_TRUNC_MPDU_TH_3_ADDR     BN1_WF_AGG_TOP_TTCR1_ADDR
#define BN1_WF_AGG_TOP_TTCR1_DYN_TXOP_TRUNC_MPDU_TH_3_MASK     0x000000FF                // DYN_TXOP_TRUNC_MPDU_TH_3[7..0]
#define BN1_WF_AGG_TOP_TTCR1_DYN_TXOP_TRUNC_MPDU_TH_3_SHFT     0

/* =====================================================================================

  ---ACR0 (0x820f2000 + 0x84)---

    CFEND0_RATE[13..0]           - (RW) Used for CF-End to truncate long NAV TXOP
                                     Rate definition is the same as BAR_RATE
    RESERVED14[15..14]           - (RO) Reserved bits
    BAR0_RATE[29..16]            - (RW) Used for BAR for life timeout or retry fail frame
                                     Bit[13]: 
                                     STBC: not support need (set to 0)
                                     Bit[12:10]: 
                                     Nsts: only support one space time stream (set to 0)
                                     
                                     Bit[9:6]: TX Mode
                                     indicate the transmission mode
                                     0000: Legacy CCK
                                     0001: Legacy OFDM
                                     0010: HT Mixed mode
                                     0011: HT Green field mode
                                     0100~1111: reserved
                                     Bit[5:0]: TX rate
                                     For Legacy CCK:
                                     CCK: (long preamble)
                                     6'b00_0000: 1M
                                     6'b00_0001: 2M
                                     6'b00_0010: 5.5M
                                     6'b00_0011: 11M
                                     CCK: (short preamble)
                                     6'b00_0101: 2M
                                     6'b00_0110: 5.5M
                                     6'b00_0111: 11M
                                     
                                     For Legacy OFDM:
                                     6'b00_1011: 6M (in 20MHz channel spacing)
                                     6'b00_1111: 9M (in 20MHz channel spacing)
                                     6'b00_1010: 12M (in 20MHz channel spacing)
                                     6'b00_1110: 18M (in 20MHz channel spacing)
                                     6'b00_1001: 24M (in 20MHz channel spacing)
                                     6'b00_1101: 36M (in 20MHz channel spacing)
                                     6'b00_1000: 48M (in 20MHz channel spacing)
                                     6'b00_1100: 54M (in 20MHz channel spacing)
                                     
                                     For HT rate:
                                     The bits 0~5 indicate MCSN, N=0~7 and 32, others reserved
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ACR0_BAR0_RATE_ADDR                     BN1_WF_AGG_TOP_ACR0_ADDR
#define BN1_WF_AGG_TOP_ACR0_BAR0_RATE_MASK                     0x3FFF0000                // BAR0_RATE[29..16]
#define BN1_WF_AGG_TOP_ACR0_BAR0_RATE_SHFT                     16
#define BN1_WF_AGG_TOP_ACR0_CFEND0_RATE_ADDR                   BN1_WF_AGG_TOP_ACR0_ADDR
#define BN1_WF_AGG_TOP_ACR0_CFEND0_RATE_MASK                   0x00003FFF                // CFEND0_RATE[13..0]
#define BN1_WF_AGG_TOP_ACR0_CFEND0_RATE_SHFT                   0

/* =====================================================================================

  ---ACR1 (0x820f2000 + 0x88)---

    AMPDU0_NO_BA_RULE[0]         - (RW) Re-transmission rule if no BA is received
                                     1'b1: When MT6620 WIFI transmits AMPDU and does not receive BA, MT6620 WIFI will retransmit AMPDU with the first MPDU.
                                     1'b0: When MT6620 WIFI transmits AMPDU and does not receive BA, MT6620 WIFI will re-transmit this AMPDU.
                                     Note: Because the current support linked lists forward search, it may cause some interference about this function, e.g. its 1st AMPDU (with 16 MPDU from WTBL_idx0) has no BA; this AC's next AMPDU only has 1 MPDU (even it is not WTBL_idx0 because of forward search).
                                     (For DBDC channel 0)
    AMPDU0_NO_BA_AR_RULE[1]      - (RW) Auto rate TX/FAIL count rule when AMPDU sent but BA not received.
                                     1'b0: count for each MPDU
                                     1'b1: count 1 only, both TX/FAIL count only added 1
                                     (for DBDC channel 0)
    FW0_PKT_TIME_EN[2]           - (RW) Enables firmware packet time
                                     For the firmware packet (PKT_FT=2'h3 in Tx descriptor), accumulate time difference into WTBL or not.
                                     1'b0: Not accumulate firmware packet's time difference into WTBL
                                     1'b1: Accumulate firmware packet's time difference into WTBL
                                     (For DBDC channel 0)
    RDG0_RESP_TX_DUR_EN[3]       - (RW) Enables RDG responder Tx duration
                                     1'b0: MIB's Tx duration contains the period that our chip is RDG responder. On the other hand, MIB's Tx duration does not contain the period that our chip, RDG initiator, reverse direction grant to the peer, RDG responder.
                                     1'b1: MIB's Tx duration does not contain the period that our chip is RDG responder. On the other hand, MIB's Tx duration will contain the period that our chip, RDG initiator, reverse direction grant to the peer, RDG responder.
                                     (For DBDC channel 0)
    GLB_LDPC_UR_EN_B0[4]         - (RW) Global LDPC Unsupport Rate control
                                     0: Disable LDPC unsupported rate function
                                     1: Enable LDPC unsupported rate function (default)
    ALWAYS_TX_RESTART_B0[5]      - (RW) Always request ARB tx restart after each SU PPDU sent out during TXOP window(for DBDC BAND0)
    IGNORE_LP_TBTT_REMAINTIME_B0[6] - (RW) Indicate AGG to hornor LP TBTT Remaining Time or not when tmac0_cr_tbtt_tx_stop_control is set
                                     0: Always hornor LP TBTT Remaining Time for current PPDU
                                     1: Ignore LP TBTT Remaining Time for current PPDU if remaining time is not equal to 0
    RESERVED7[15..7]             - (RO) Reserved bits
    CFEND0_SPE_IDX[20..16]       - (RW) Spatial extension index used for CF-End to truncate long NAV TXOP
                                     (For DBDC channel 0)
    RESERVED21[23..21]           - (RO) Reserved bits
    BAR0_SPE_IDX[28..24]         - (RW) Spatial extension index used for BAR of life timeout or retry fail frame
                                     (For DBDC channel 0)
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ACR1_BAR0_SPE_IDX_ADDR                  BN1_WF_AGG_TOP_ACR1_ADDR
#define BN1_WF_AGG_TOP_ACR1_BAR0_SPE_IDX_MASK                  0x1F000000                // BAR0_SPE_IDX[28..24]
#define BN1_WF_AGG_TOP_ACR1_BAR0_SPE_IDX_SHFT                  24
#define BN1_WF_AGG_TOP_ACR1_CFEND0_SPE_IDX_ADDR                BN1_WF_AGG_TOP_ACR1_ADDR
#define BN1_WF_AGG_TOP_ACR1_CFEND0_SPE_IDX_MASK                0x001F0000                // CFEND0_SPE_IDX[20..16]
#define BN1_WF_AGG_TOP_ACR1_CFEND0_SPE_IDX_SHFT                16
#define BN1_WF_AGG_TOP_ACR1_IGNORE_LP_TBTT_REMAINTIME_B0_ADDR  BN1_WF_AGG_TOP_ACR1_ADDR
#define BN1_WF_AGG_TOP_ACR1_IGNORE_LP_TBTT_REMAINTIME_B0_MASK  0x00000040                // IGNORE_LP_TBTT_REMAINTIME_B0[6]
#define BN1_WF_AGG_TOP_ACR1_IGNORE_LP_TBTT_REMAINTIME_B0_SHFT  6
#define BN1_WF_AGG_TOP_ACR1_ALWAYS_TX_RESTART_B0_ADDR          BN1_WF_AGG_TOP_ACR1_ADDR
#define BN1_WF_AGG_TOP_ACR1_ALWAYS_TX_RESTART_B0_MASK          0x00000020                // ALWAYS_TX_RESTART_B0[5]
#define BN1_WF_AGG_TOP_ACR1_ALWAYS_TX_RESTART_B0_SHFT          5
#define BN1_WF_AGG_TOP_ACR1_GLB_LDPC_UR_EN_B0_ADDR             BN1_WF_AGG_TOP_ACR1_ADDR
#define BN1_WF_AGG_TOP_ACR1_GLB_LDPC_UR_EN_B0_MASK             0x00000010                // GLB_LDPC_UR_EN_B0[4]
#define BN1_WF_AGG_TOP_ACR1_GLB_LDPC_UR_EN_B0_SHFT             4
#define BN1_WF_AGG_TOP_ACR1_RDG0_RESP_TX_DUR_EN_ADDR           BN1_WF_AGG_TOP_ACR1_ADDR
#define BN1_WF_AGG_TOP_ACR1_RDG0_RESP_TX_DUR_EN_MASK           0x00000008                // RDG0_RESP_TX_DUR_EN[3]
#define BN1_WF_AGG_TOP_ACR1_RDG0_RESP_TX_DUR_EN_SHFT           3
#define BN1_WF_AGG_TOP_ACR1_FW0_PKT_TIME_EN_ADDR               BN1_WF_AGG_TOP_ACR1_ADDR
#define BN1_WF_AGG_TOP_ACR1_FW0_PKT_TIME_EN_MASK               0x00000004                // FW0_PKT_TIME_EN[2]
#define BN1_WF_AGG_TOP_ACR1_FW0_PKT_TIME_EN_SHFT               2
#define BN1_WF_AGG_TOP_ACR1_AMPDU0_NO_BA_AR_RULE_ADDR          BN1_WF_AGG_TOP_ACR1_ADDR
#define BN1_WF_AGG_TOP_ACR1_AMPDU0_NO_BA_AR_RULE_MASK          0x00000002                // AMPDU0_NO_BA_AR_RULE[1]
#define BN1_WF_AGG_TOP_ACR1_AMPDU0_NO_BA_AR_RULE_SHFT          1
#define BN1_WF_AGG_TOP_ACR1_AMPDU0_NO_BA_RULE_ADDR             BN1_WF_AGG_TOP_ACR1_ADDR
#define BN1_WF_AGG_TOP_ACR1_AMPDU0_NO_BA_RULE_MASK             0x00000001                // AMPDU0_NO_BA_RULE[0]
#define BN1_WF_AGG_TOP_ACR1_AMPDU0_NO_BA_RULE_SHFT             0

/* =====================================================================================

  ---ACR4 (0x820f2000 + 0x8c)---

    PPDU_TXS2M_EN_B0[0]          - (RW) PPDU Status TO MCU Enable
                                     0: Disable
                                     1: Report PPDU status to MCU for each PPDU no matter success or not
    PPDU_TXS2H_EN_B0[1]          - (RW) PPDU Status To Host Enable
                                     0: Disable
                                     1: Report PPDU status to Host for each PPDU no matter success or not
    RESERVED2[31..2]             - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ACR4_PPDU_TXS2H_EN_B0_ADDR              BN1_WF_AGG_TOP_ACR4_ADDR
#define BN1_WF_AGG_TOP_ACR4_PPDU_TXS2H_EN_B0_MASK              0x00000002                // PPDU_TXS2H_EN_B0[1]
#define BN1_WF_AGG_TOP_ACR4_PPDU_TXS2H_EN_B0_SHFT              1
#define BN1_WF_AGG_TOP_ACR4_PPDU_TXS2M_EN_B0_ADDR              BN1_WF_AGG_TOP_ACR4_ADDR
#define BN1_WF_AGG_TOP_ACR4_PPDU_TXS2M_EN_B0_MASK              0x00000001                // PPDU_TXS2M_EN_B0[0]
#define BN1_WF_AGG_TOP_ACR4_PPDU_TXS2M_EN_B0_SHFT              0

/* =====================================================================================

  ---ACR6 (0x820f2000 + 0x90)---

    RESERVED0[0]                 - (RO) Reserved bits
    CCK_PROTECT_OVER_BW20_1ST[1] - (RW) CCK protect over bandwidth 20 for first TXD
                                     1'b0: Can only Tx packet with BW20 in the following TXOP
                                     1'b1: Packet has no bandwidth limitation in the following TXOP.
                                     (If the following TXD meets RTS_PKT_NUM_THRESHOLD or RTS_PKT_LEN_THRESHOLD, HW will give up the last aggregation to avoid protect packet issues.)
    CCK_PROTECT_OVER_BW20_ALL[2] - (RW) CCK protect over bandwidth 20 for all TXD
                                     1'b0: Can only Tx packet with BW20 in the following TXOP
                                     1'b1: Packet has no bandwidth limitation in the following TXOP.
    NLNAV_MID_PTEC_DIS[3]        - (RW) Disables non-long NAV middle protect
                                     1'b0: If protect is enabled (PCR0~1), issue protection packet for each PPDU.
                                     1'b1: If protect is enabled (PCR0~1), only issue protection packet for TXOP initiation. Not issue protect packet for the following PPDU.
    RESERVED4[5..4]              - (RO) Reserved bits
    ALWAYS_RLS_QUE[6]            - (RW) Always release 64 bitmap index to PLE
                                     0: enable(default)
                                     1: disable(might has bug)
    TXS_DISABLE[7]               - (RW) Set 1 to disable upload TXS
    RESERVED8[9..8]              - (RO) Reserved bits
    HW_BAR_DIS_TXOP[10]          - (RW) 0: Allow HW BAR Packet to initiate TXOP
                                     1: Not allow HW BAR Packet to initiate TXOP
    NON_QOSDATA_DIS_TXOP[11]     - (RW) 0: Allow Non-QoS Packet to initiate TXOP
                                     1: Not allow Non-QoS Packet to initiate TXOP
    FIX_RATE_DIS_TXOP[12]        - (RW) 0: Allow Fixed Rate Packet to initiate TXOP
                                     1: Not allow Fixed Rate Packet to initiate TXOP
    RTS_FAIL_WTBL_TXCNT_MODE[13] - (RW) RTS Fail WTBL TXCNT MODE
                                     0: WTBL TX/FAIL counter add one when RTS fail reach limit 
                                     1: WTBL TX/FAIL counter add one when RTS fail
    RTS_FAIL_DROP_MODE[14]       - (RW) RTS DROP MODE
                                     0: Only drop one MPDU when RTS fail reach limit 
                                     1: Drop all MPDU inside BA_WIN_SIZE when RTS fail reach limit
    RESERVED15[15]               - (RO) Reserved bits
    SN_WB_MODE[16]               - (RW) SN write back mode
                                     PN/SN/TXCNT/REMTXCNT writes back to descriptor to wait for MAC2PHY TX or not
                                     0: Wait for MAC2PHY TX; will not interfere packet retry count 
                                     1: Not wait for MAC2PHY TX; may interfere packet retry count
    RESERVED17[19..17]           - (RO) Reserved bits
    BUSY_START_ABORT_EN[20]      - (RW) If ARB backoff times out but AGG state machine is busy, enable extra abort.
                                     0: No extra abort
                                     1: Extra abort
    RESERVED21[25..21]           - (RO) Reserved bits
    NOT_IDLE_MODE[26]            - (RW) AGG not idle mode. agg0/1_not_idle consider UMAC abort pending or not.
                                     0: if AGG's state machine busy, AGG will assert agg0/1_not_idle (original design)
                                     1: if AGG's state machine busy or UMAC abort unfinish, AGG will assert agg0/1_not_idle
    DMA_NOT_IDLE_MODE[27]        - (RW) AGG not idle mode. agg0/1_not_idle consider DMA is waiting buffer to upload TXS or not.
                                     0: if AGG's state machine busy and DMA is waiting buffer, AGG will de-assert agg0/1_not_idle (default)
                                     1: if AGG's state machine busy, AGG will assert agg0/1_not_idle no matter  DMA is waiting buffer or not
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ACR6_DMA_NOT_IDLE_MODE_ADDR             BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_DMA_NOT_IDLE_MODE_MASK             0x08000000                // DMA_NOT_IDLE_MODE[27]
#define BN1_WF_AGG_TOP_ACR6_DMA_NOT_IDLE_MODE_SHFT             27
#define BN1_WF_AGG_TOP_ACR6_NOT_IDLE_MODE_ADDR                 BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_NOT_IDLE_MODE_MASK                 0x04000000                // NOT_IDLE_MODE[26]
#define BN1_WF_AGG_TOP_ACR6_NOT_IDLE_MODE_SHFT                 26
#define BN1_WF_AGG_TOP_ACR6_BUSY_START_ABORT_EN_ADDR           BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_BUSY_START_ABORT_EN_MASK           0x00100000                // BUSY_START_ABORT_EN[20]
#define BN1_WF_AGG_TOP_ACR6_BUSY_START_ABORT_EN_SHFT           20
#define BN1_WF_AGG_TOP_ACR6_SN_WB_MODE_ADDR                    BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_SN_WB_MODE_MASK                    0x00010000                // SN_WB_MODE[16]
#define BN1_WF_AGG_TOP_ACR6_SN_WB_MODE_SHFT                    16
#define BN1_WF_AGG_TOP_ACR6_RTS_FAIL_DROP_MODE_ADDR            BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_RTS_FAIL_DROP_MODE_MASK            0x00004000                // RTS_FAIL_DROP_MODE[14]
#define BN1_WF_AGG_TOP_ACR6_RTS_FAIL_DROP_MODE_SHFT            14
#define BN1_WF_AGG_TOP_ACR6_RTS_FAIL_WTBL_TXCNT_MODE_ADDR      BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_RTS_FAIL_WTBL_TXCNT_MODE_MASK      0x00002000                // RTS_FAIL_WTBL_TXCNT_MODE[13]
#define BN1_WF_AGG_TOP_ACR6_RTS_FAIL_WTBL_TXCNT_MODE_SHFT      13
#define BN1_WF_AGG_TOP_ACR6_FIX_RATE_DIS_TXOP_ADDR             BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_FIX_RATE_DIS_TXOP_MASK             0x00001000                // FIX_RATE_DIS_TXOP[12]
#define BN1_WF_AGG_TOP_ACR6_FIX_RATE_DIS_TXOP_SHFT             12
#define BN1_WF_AGG_TOP_ACR6_NON_QOSDATA_DIS_TXOP_ADDR          BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_NON_QOSDATA_DIS_TXOP_MASK          0x00000800                // NON_QOSDATA_DIS_TXOP[11]
#define BN1_WF_AGG_TOP_ACR6_NON_QOSDATA_DIS_TXOP_SHFT          11
#define BN1_WF_AGG_TOP_ACR6_HW_BAR_DIS_TXOP_ADDR               BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_HW_BAR_DIS_TXOP_MASK               0x00000400                // HW_BAR_DIS_TXOP[10]
#define BN1_WF_AGG_TOP_ACR6_HW_BAR_DIS_TXOP_SHFT               10
#define BN1_WF_AGG_TOP_ACR6_TXS_DISABLE_ADDR                   BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_TXS_DISABLE_MASK                   0x00000080                // TXS_DISABLE[7]
#define BN1_WF_AGG_TOP_ACR6_TXS_DISABLE_SHFT                   7
#define BN1_WF_AGG_TOP_ACR6_ALWAYS_RLS_QUE_ADDR                BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_ALWAYS_RLS_QUE_MASK                0x00000040                // ALWAYS_RLS_QUE[6]
#define BN1_WF_AGG_TOP_ACR6_ALWAYS_RLS_QUE_SHFT                6
#define BN1_WF_AGG_TOP_ACR6_NLNAV_MID_PTEC_DIS_ADDR            BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_NLNAV_MID_PTEC_DIS_MASK            0x00000008                // NLNAV_MID_PTEC_DIS[3]
#define BN1_WF_AGG_TOP_ACR6_NLNAV_MID_PTEC_DIS_SHFT            3
#define BN1_WF_AGG_TOP_ACR6_CCK_PROTECT_OVER_BW20_ALL_ADDR     BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_CCK_PROTECT_OVER_BW20_ALL_MASK     0x00000004                // CCK_PROTECT_OVER_BW20_ALL[2]
#define BN1_WF_AGG_TOP_ACR6_CCK_PROTECT_OVER_BW20_ALL_SHFT     2
#define BN1_WF_AGG_TOP_ACR6_CCK_PROTECT_OVER_BW20_1ST_ADDR     BN1_WF_AGG_TOP_ACR6_ADDR
#define BN1_WF_AGG_TOP_ACR6_CCK_PROTECT_OVER_BW20_1ST_MASK     0x00000002                // CCK_PROTECT_OVER_BW20_1ST[1]
#define BN1_WF_AGG_TOP_ACR6_CCK_PROTECT_OVER_BW20_1ST_SHFT     1

/* =====================================================================================

  ---ACR7 (0x820f2000 + 0x94)---

    CTL_FRAME0_ANT_ID[23..0]     - (RW) Control packet (CFEnd, BAR) antenna ID
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ACR7_CTL_FRAME0_ANT_ID_ADDR             BN1_WF_AGG_TOP_ACR7_ADDR
#define BN1_WF_AGG_TOP_ACR7_CTL_FRAME0_ANT_ID_MASK             0x00FFFFFF                // CTL_FRAME0_ANT_ID[23..0]
#define BN1_WF_AGG_TOP_ACR7_CTL_FRAME0_ANT_ID_SHFT             0

/* =====================================================================================

  ---MRCR (0x820f2000 + 0x98)---

    RTY_MODE0[1..0]              - (RW) Tx retry mode
                                     2'h0: When Tx fails, TMAC enters I2T then Tx.
                                     2'h1: When Tx fails, TMAC enters R2T then Tx.
                                     2'h2: When Tx fails, AGG waits for slot_idle then Tx.
                                     2'h3: Reserved
    RESERVED2[5..2]              - (RO) Reserved bits
    LAST_RTS_AS_CTS_EN[6]        - (RW) Replace last RTS with CTS2Self enable
                                     1'b0: disable this function
                                     1'b1: depend on RTS_RTY_CNT_LIMIT, the last protection use CTS2Self
                                     (if enable this function and RTS_RTY_CNT_LIMIT=0, don't protect by RTS and only protect by CTS2Self.)
    RTS_FAIL_CNT_LIMIT[11..7]    - (RW) RTS fail count limit for none BA or BA enabled MPDU
                                     A none BA or BA enabled MPDU will be released as RTS error when it needs RTS and RTS fail count reaches this value.
                                     4'd0: Unlimited; 
                                     4'd1~4'd31: Send RTS until this TX limit is reached
    BAR_TX_CNT_LIMIT[15..12]     - (RW) BAR frame TX count limit
                                     Used for BA enabled frame and life timeout
                                     4'd0: No BAR, release directly.
                                     4'd1~4'd15: Send BAR until this TX limit is reached
    RESERVED16[23..16]           - (RO) Reserved bits
    TXCMD_RTS_FAIL_CNT_LIMIT[28..24] - (RW) RTS fail count limit for TXCMD.
                                     TXCMD will be released as RTS error when it needs RTS and RTS fail count reaches this value.
                                     4'd0: Unlimited; 
                                     4'd1~4'd31: Send RTS until this TX limit is reached
    RESERVED29[31..29]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_MRCR_TXCMD_RTS_FAIL_CNT_LIMIT_ADDR      BN1_WF_AGG_TOP_MRCR_ADDR
#define BN1_WF_AGG_TOP_MRCR_TXCMD_RTS_FAIL_CNT_LIMIT_MASK      0x1F000000                // TXCMD_RTS_FAIL_CNT_LIMIT[28..24]
#define BN1_WF_AGG_TOP_MRCR_TXCMD_RTS_FAIL_CNT_LIMIT_SHFT      24
#define BN1_WF_AGG_TOP_MRCR_BAR_TX_CNT_LIMIT_ADDR              BN1_WF_AGG_TOP_MRCR_ADDR
#define BN1_WF_AGG_TOP_MRCR_BAR_TX_CNT_LIMIT_MASK              0x0000F000                // BAR_TX_CNT_LIMIT[15..12]
#define BN1_WF_AGG_TOP_MRCR_BAR_TX_CNT_LIMIT_SHFT              12
#define BN1_WF_AGG_TOP_MRCR_RTS_FAIL_CNT_LIMIT_ADDR            BN1_WF_AGG_TOP_MRCR_ADDR
#define BN1_WF_AGG_TOP_MRCR_RTS_FAIL_CNT_LIMIT_MASK            0x00000F80                // RTS_FAIL_CNT_LIMIT[11..7]
#define BN1_WF_AGG_TOP_MRCR_RTS_FAIL_CNT_LIMIT_SHFT            7
#define BN1_WF_AGG_TOP_MRCR_LAST_RTS_AS_CTS_EN_ADDR            BN1_WF_AGG_TOP_MRCR_ADDR
#define BN1_WF_AGG_TOP_MRCR_LAST_RTS_AS_CTS_EN_MASK            0x00000040                // LAST_RTS_AS_CTS_EN[6]
#define BN1_WF_AGG_TOP_MRCR_LAST_RTS_AS_CTS_EN_SHFT            6
#define BN1_WF_AGG_TOP_MRCR_RTY_MODE0_ADDR                     BN1_WF_AGG_TOP_MRCR_ADDR
#define BN1_WF_AGG_TOP_MRCR_RTY_MODE0_MASK                     0x00000003                // RTY_MODE0[1..0]
#define BN1_WF_AGG_TOP_MRCR_RTY_MODE0_SHFT                     0

/* =====================================================================================

  ---BTIMRR0 (0x820f2000 + 0x9c)---

    BTIM_RATE0[9..0]             - (RW) TIM broadcast rate for OM=0x00 (BSSID0)
                                     Assume STBC = 0 and Nsts = 0,
                                     Bit[9:6]: TX mode
                                     Indicates transmission mode
                                     4'b0000: Legacy CCK  001: Legacy OFDM
                                     4'b0010: HT mixed mode  011: HT green field mode
                                     4'b0100: VHT mode
                                     4'b1000: HE_SU
                                     4'b1001: HE_EXT_SU
                                     4'b1010: HE_TRIG
                                     4'b1011: HE_MU
                                     1100~1111: reserved
                                     Bit[5:0]: TX rate
                                     For Legacy CCK:
                                     CCK: (long preamble)
                                     6'b00_0000: 1M   6'b00_0001: 2M
                                     6'b00_0010: 5.5M  6'b00_0011: 11M
                                     CCK: (short preamble)
                                     6'b00_0101: 2M   6'b00_0110: 5.5M
                                     6'b00_0111: 11M
                                     For Legacy OFDM:
                                     6'b00_1011: 6M (in 20MHz channel spacing)
                                     6'b00_1111: 9M (in 20MHz channel spacing)
                                     6'b00_1010: 12M (in 20MHz channel spacing)
                                     6'b00_1110: 18M (in 20MHz channel spacing)
                                     6'b00_1001: 24M (in 20MHz channel spacing)
                                     6'b00_1101: 36M (in 20MHz channel spacing)
                                     6'b00_1000: 48M (in 20MHz channel spacing)
                                     6'b00_1100: 54M (in 20MHz channel spacing)
                                     For HT rate:
                                     Bit0~5 indicate MCSN, N=0~32; others reserved.
                                     For VHT rate:
                                     Bit0~5 indicate MCSN, N=0~9; others reserved.
                                     For HE rate:
                                     Bit0~5 indicate MCSN, N=0~9; others reserved.
    RESERVED10[15..10]           - (RO) Reserved bits
    BTIM_RATE1[25..16]           - (RW) TIM broadcast rate for OM=0x01 (BSSID1)
                                     Same as BTIM_RATE0.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_BTIMRR0_BTIM_RATE1_ADDR                 BN1_WF_AGG_TOP_BTIMRR0_ADDR
#define BN1_WF_AGG_TOP_BTIMRR0_BTIM_RATE1_MASK                 0x03FF0000                // BTIM_RATE1[25..16]
#define BN1_WF_AGG_TOP_BTIMRR0_BTIM_RATE1_SHFT                 16
#define BN1_WF_AGG_TOP_BTIMRR0_BTIM_RATE0_ADDR                 BN1_WF_AGG_TOP_BTIMRR0_ADDR
#define BN1_WF_AGG_TOP_BTIMRR0_BTIM_RATE0_MASK                 0x000003FF                // BTIM_RATE0[9..0]
#define BN1_WF_AGG_TOP_BTIMRR0_BTIM_RATE0_SHFT                 0

/* =====================================================================================

  ---BTIMRR1 (0x820f2000 + 0xa0)---

    BTIM_RATE2[9..0]             - (RW) TIM broadcast rate for OM=0x02 (BSSID2)
                                     Same as BTIM_RATE0.
    RESERVED10[15..10]           - (RO) Reserved bits
    BTIM_RATE3[25..16]           - (RW) TIM broadcast rate for OM=0x03 (BSSID3)
                                     Same as BTIM_RATE0.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_BTIMRR1_BTIM_RATE3_ADDR                 BN1_WF_AGG_TOP_BTIMRR1_ADDR
#define BN1_WF_AGG_TOP_BTIMRR1_BTIM_RATE3_MASK                 0x03FF0000                // BTIM_RATE3[25..16]
#define BN1_WF_AGG_TOP_BTIMRR1_BTIM_RATE3_SHFT                 16
#define BN1_WF_AGG_TOP_BTIMRR1_BTIM_RATE2_ADDR                 BN1_WF_AGG_TOP_BTIMRR1_ADDR
#define BN1_WF_AGG_TOP_BTIMRR1_BTIM_RATE2_MASK                 0x000003FF                // BTIM_RATE2[9..0]
#define BN1_WF_AGG_TOP_BTIMRR1_BTIM_RATE2_SHFT                 0

/* =====================================================================================

  ---BTIMRR2 (0x820f2000 + 0xa4)---

    RESERVED0[15..0]             - (RO) Reserved bits
    BTIM_RATE0_1[25..16]         - (RW) TIM broadcast rate for OM=0x11 (BSSID0_1)
                                     Same as BTIM_RATE0.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_BTIMRR2_BTIM_RATE0_1_ADDR               BN1_WF_AGG_TOP_BTIMRR2_ADDR
#define BN1_WF_AGG_TOP_BTIMRR2_BTIM_RATE0_1_MASK               0x03FF0000                // BTIM_RATE0_1[25..16]
#define BN1_WF_AGG_TOP_BTIMRR2_BTIM_RATE0_1_SHFT               16

/* =====================================================================================

  ---BTIMRR3 (0x820f2000 + 0xa8)---

    BTIM_RATE0_2[9..0]           - (RW) TIM broadcast rate for OM=0x12 (BSSID0_2)
                                     Same as BTIM_RATE0.
    RESERVED10[15..10]           - (RO) Reserved bits
    BTIM_RATE0_3[25..16]         - (RW) TIM broadcast rate for OM=0x13 (BSSID0_3)
                                     Same as BTIM_RATE0.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_BTIMRR3_BTIM_RATE0_3_ADDR               BN1_WF_AGG_TOP_BTIMRR3_ADDR
#define BN1_WF_AGG_TOP_BTIMRR3_BTIM_RATE0_3_MASK               0x03FF0000                // BTIM_RATE0_3[25..16]
#define BN1_WF_AGG_TOP_BTIMRR3_BTIM_RATE0_3_SHFT               16
#define BN1_WF_AGG_TOP_BTIMRR3_BTIM_RATE0_2_ADDR               BN1_WF_AGG_TOP_BTIMRR3_ADDR
#define BN1_WF_AGG_TOP_BTIMRR3_BTIM_RATE0_2_MASK               0x000003FF                // BTIM_RATE0_2[9..0]
#define BN1_WF_AGG_TOP_BTIMRR3_BTIM_RATE0_2_SHFT               0

/* =====================================================================================

  ---BTIMRR4 (0x820f2000 + 0xac)---

    BTIM_RATE0_4[9..0]           - (RW) TIM broadcast rate for OM=0x14 (BSSID0_4)
                                     Same as BTIM_RATE0.
    RESERVED10[15..10]           - (RO) Reserved bits
    BTIM_RATE0_5[25..16]         - (RW) TIM broadcast rate for OM=0x15 (BSSID0_5)
                                     Same as BTIM_RATE0.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_BTIMRR4_BTIM_RATE0_5_ADDR               BN1_WF_AGG_TOP_BTIMRR4_ADDR
#define BN1_WF_AGG_TOP_BTIMRR4_BTIM_RATE0_5_MASK               0x03FF0000                // BTIM_RATE0_5[25..16]
#define BN1_WF_AGG_TOP_BTIMRR4_BTIM_RATE0_5_SHFT               16
#define BN1_WF_AGG_TOP_BTIMRR4_BTIM_RATE0_4_ADDR               BN1_WF_AGG_TOP_BTIMRR4_ADDR
#define BN1_WF_AGG_TOP_BTIMRR4_BTIM_RATE0_4_MASK               0x000003FF                // BTIM_RATE0_4[9..0]
#define BN1_WF_AGG_TOP_BTIMRR4_BTIM_RATE0_4_SHFT               0

/* =====================================================================================

  ---BTIMRR5 (0x820f2000 + 0xb0)---

    BTIM_RATE0_6[9..0]           - (RW) TIM broadcast rate for OM=0x16 (BSSID0_6)
                                     Same as BTIM_RATE0.
    RESERVED10[15..10]           - (RO) Reserved bits
    BTIM_RATE0_7[25..16]         - (RW) TIM broadcast rate for OM=0x17 (BSSID0_7)
                                     Same as BTIM_RATE0.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_BTIMRR5_BTIM_RATE0_7_ADDR               BN1_WF_AGG_TOP_BTIMRR5_ADDR
#define BN1_WF_AGG_TOP_BTIMRR5_BTIM_RATE0_7_MASK               0x03FF0000                // BTIM_RATE0_7[25..16]
#define BN1_WF_AGG_TOP_BTIMRR5_BTIM_RATE0_7_SHFT               16
#define BN1_WF_AGG_TOP_BTIMRR5_BTIM_RATE0_6_ADDR               BN1_WF_AGG_TOP_BTIMRR5_ADDR
#define BN1_WF_AGG_TOP_BTIMRR5_BTIM_RATE0_6_MASK               0x000003FF                // BTIM_RATE0_6[9..0]
#define BN1_WF_AGG_TOP_BTIMRR5_BTIM_RATE0_6_SHFT               0

/* =====================================================================================

  ---BTIMRR6 (0x820f2000 + 0xb4)---

    BTIM_RATE0_8[9..0]           - (RW) TIM broadcast rate for OM=0x18 (BSSID0_8)
                                     Same as BTIM_RATE0.
    RESERVED10[15..10]           - (RO) Reserved bits
    BTIM_RATE0_9[25..16]         - (RW) TIM broadcast rate for OM=0x19 (BSSID0_9)
                                     Same as BTIM_RATE0.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_BTIMRR6_BTIM_RATE0_9_ADDR               BN1_WF_AGG_TOP_BTIMRR6_ADDR
#define BN1_WF_AGG_TOP_BTIMRR6_BTIM_RATE0_9_MASK               0x03FF0000                // BTIM_RATE0_9[25..16]
#define BN1_WF_AGG_TOP_BTIMRR6_BTIM_RATE0_9_SHFT               16
#define BN1_WF_AGG_TOP_BTIMRR6_BTIM_RATE0_8_ADDR               BN1_WF_AGG_TOP_BTIMRR6_ADDR
#define BN1_WF_AGG_TOP_BTIMRR6_BTIM_RATE0_8_MASK               0x000003FF                // BTIM_RATE0_8[9..0]
#define BN1_WF_AGG_TOP_BTIMRR6_BTIM_RATE0_8_SHFT               0

/* =====================================================================================

  ---BTIMRR7 (0x820f2000 + 0xb8)---

    BTIM_RATE0_A[9..0]           - (RW) TIM broadcast rate for OM=0x1A (BSSID0_A)
                                     Same as BTIM_RATE0.
    RESERVED10[15..10]           - (RO) Reserved bits
    BTIM_RATE0_B[25..16]         - (RW) TIM broadcast rate for OM=0x1B (BSSID0_B)
                                     Same as BTIM_RATE0.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_BTIMRR7_BTIM_RATE0_B_ADDR               BN1_WF_AGG_TOP_BTIMRR7_ADDR
#define BN1_WF_AGG_TOP_BTIMRR7_BTIM_RATE0_B_MASK               0x03FF0000                // BTIM_RATE0_B[25..16]
#define BN1_WF_AGG_TOP_BTIMRR7_BTIM_RATE0_B_SHFT               16
#define BN1_WF_AGG_TOP_BTIMRR7_BTIM_RATE0_A_ADDR               BN1_WF_AGG_TOP_BTIMRR7_ADDR
#define BN1_WF_AGG_TOP_BTIMRR7_BTIM_RATE0_A_MASK               0x000003FF                // BTIM_RATE0_A[9..0]
#define BN1_WF_AGG_TOP_BTIMRR7_BTIM_RATE0_A_SHFT               0

/* =====================================================================================

  ---BTIMRR8 (0x820f2000 + 0xbc)---

    BTIM_RATE0_C[9..0]           - (RW) TIM broadcast rate for OM=0x1C (BSSID0_C)
                                     Same as BTIM_RATE0.
    RESERVED10[15..10]           - (RO) Reserved bits
    BTIM_RATE0_D[25..16]         - (RW) TIM broadcast rate for OM=0x1D (BSSID0_D)
                                     Same as BTIM_RATE0.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_BTIMRR8_BTIM_RATE0_D_ADDR               BN1_WF_AGG_TOP_BTIMRR8_ADDR
#define BN1_WF_AGG_TOP_BTIMRR8_BTIM_RATE0_D_MASK               0x03FF0000                // BTIM_RATE0_D[25..16]
#define BN1_WF_AGG_TOP_BTIMRR8_BTIM_RATE0_D_SHFT               16
#define BN1_WF_AGG_TOP_BTIMRR8_BTIM_RATE0_C_ADDR               BN1_WF_AGG_TOP_BTIMRR8_ADDR
#define BN1_WF_AGG_TOP_BTIMRR8_BTIM_RATE0_C_MASK               0x000003FF                // BTIM_RATE0_C[9..0]
#define BN1_WF_AGG_TOP_BTIMRR8_BTIM_RATE0_C_SHFT               0

/* =====================================================================================

  ---BTIMRR9 (0x820f2000 + 0xc0)---

    RESERVED0[15..0]             - (RO) Reserved bits
    BTIM_RATE0_F[25..16]         - (RW) TIM broadcast rate for OM=0x1F (BSSID0_F)
                                     Same as BTIM_RATE0.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_BTIMRR9_BTIM_RATE0_F_ADDR               BN1_WF_AGG_TOP_BTIMRR9_ADDR
#define BN1_WF_AGG_TOP_BTIMRR9_BTIM_RATE0_F_MASK               0x03FF0000                // BTIM_RATE0_F[25..16]
#define BN1_WF_AGG_TOP_BTIMRR9_BTIM_RATE0_F_SHFT               16

/* =====================================================================================

  ---LBCR (0x820f2000 + 0xc4)---

    LB_MAX_AMPDU_LEN[21..0]      - (RW) Loop Back Maximum AMPDU Length.
    RESERVED22[31..22]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_LBCR_LB_MAX_AMPDU_LEN_ADDR              BN1_WF_AGG_TOP_LBCR_ADDR
#define BN1_WF_AGG_TOP_LBCR_LB_MAX_AMPDU_LEN_MASK              0x003FFFFF                // LB_MAX_AMPDU_LEN[21..0]
#define BN1_WF_AGG_TOP_LBCR_LB_MAX_AMPDU_LEN_SHFT              0

/* =====================================================================================

  ---MMPDR (0x820f2000 + 0xc8)---

    MAX_MM_PSDU_DUR0[14..0]      - (RW) Maximum mix mode PSDU duration (us) for aggregation
                                     For normal Tx: 5444us
                                     (4095 bytes*8 bits/6Mbps = 5460us)
                                     (5460 - 40 (HT header) = 5420)
                                     For J mode 10: 10888us
                                     (4095 bytes*8 bits/6Mbps*2 = 10920us)
                                     (10920 - 32 (HT header) = 10888)
                                     For J mode 5: 21776us
                                     (4095 bytes*8 bits/6Mbps*4 = 21840us)
                                     (21840 - 64 (HT header) = 21776)
    RESERVED15[31..15]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_MMPDR_MAX_MM_PSDU_DUR0_ADDR             BN1_WF_AGG_TOP_MMPDR_ADDR
#define BN1_WF_AGG_TOP_MMPDR_MAX_MM_PSDU_DUR0_MASK             0x00007FFF                // MAX_MM_PSDU_DUR0[14..0]
#define BN1_WF_AGG_TOP_MMPDR_MAX_MM_PSDU_DUR0_SHFT             0

/* =====================================================================================

  ---GFPDR (0x820f2000 + 0xcc)---

    MAX_GF_PSDU_DUR0[14..0]      - (RW) Maximum green Field PSDU duration (us) for aggregation
                                     For normal Tx: 9968us
                                     (10000 - 52 (HT header) = 9948)
                                     For J mode 10: 19936us
                                     (20000 - 64 (HT header) = 19936)
                                     For J mode 5: 32639us
                                     (32767 - 128 (HT header) = 32639)
    RESERVED15[31..15]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_GFPDR_MAX_GF_PSDU_DUR0_ADDR             BN1_WF_AGG_TOP_GFPDR_ADDR
#define BN1_WF_AGG_TOP_GFPDR_MAX_GF_PSDU_DUR0_MASK             0x00007FFF                // MAX_GF_PSDU_DUR0[14..0]
#define BN1_WF_AGG_TOP_GFPDR_MAX_GF_PSDU_DUR0_SHFT             0

/* =====================================================================================

  ---VHTPDR (0x820f2000 + 0xd0)---

    MAX_VHT_PSDU_DUR0[14..0]     - (RW) Maximum VHT PSDU duration (us) for aggregation
                                     For normal Tx: 5440us
                                     (4095 bytes*8 bits/6Mbps = 5460us)
                                     (5460 - 44 (VHT header) = 5416)
                                     For TVWS 8M: 19887us
                                     (20000 - 20*5.625 = 19887.5)
                                     For TVWS 6M or 7M: 19850us
                                     (20000 - 20*7.5 = 19850)
                                     For J mode 10: 10880us
                                     (4095 bytes*8 bits/6Mbps*2 = 10920us)
                                     (10920 - 40 (HT header) = 10880)
                                     For J mode 5: 21760us
                                     (4095 bytes*8 bits/6Mbps*4 = 21840us)
                                     (21840 - 80 (HT header) = 21760)
    RESERVED15[31..15]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_VHTPDR_MAX_VHT_PSDU_DUR0_ADDR           BN1_WF_AGG_TOP_VHTPDR_ADDR
#define BN1_WF_AGG_TOP_VHTPDR_MAX_VHT_PSDU_DUR0_MASK           0x00007FFF                // MAX_VHT_PSDU_DUR0[14..0]
#define BN1_WF_AGG_TOP_VHTPDR_MAX_VHT_PSDU_DUR0_SHFT           0

/* =====================================================================================

  ---HEPDR (0x820f2000 + 0xd4)---

    MAX_HE_PSDU_DUR0[14..0]      - (RW) Maximum VHT PSDU duration (us) for aggregation
                                     For normal Tx: 5440us
                                     (4095 bytes*8 bits/6Mbps = 5460us)
                                     (5460 - 44 (VHT header) = 5416)
                                     For TVWS 8M: 19887us
                                     (20000 - 20*5.625 = 19887.5)
                                     For TVWS 6M or 7M: 19850us
                                     (20000 - 20*7.5 = 19850)
                                     For J mode 10: 10880us
                                     (4095 bytes*8 bits/6Mbps*2 = 10920us)
                                     (10920 - 40 (HT header) = 10880)
                                     For J mode 5: 21760us
                                     (4095 bytes*8 bits/6Mbps*4 = 21840us)
                                     (21840 - 80 (HT header) = 21760)
    RESERVED15[31..15]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_HEPDR_MAX_HE_PSDU_DUR0_ADDR             BN1_WF_AGG_TOP_HEPDR_ADDR
#define BN1_WF_AGG_TOP_HEPDR_MAX_HE_PSDU_DUR0_MASK             0x00007FFF                // MAX_HE_PSDU_DUR0[14..0]
#define BN1_WF_AGG_TOP_HEPDR_MAX_HE_PSDU_DUR0_SHFT             0

/* =====================================================================================

  ---MUCR0 (0x820f2000 + 0xd8)---

    RESERVED0[13..0]             - (RO) Reserved bits
    MU_DYNBW_EN_B0[14]           - (RW) Enables MU dynamic bandwidth
    RESERVED15[15]               - (RO) Reserved bits
    MU_SPE_IDX_B0[20..16]        - (RW) Spatial extension index used for MU
    RESERVED21[31..21]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_MUCR0_MU_SPE_IDX_B0_ADDR                BN1_WF_AGG_TOP_MUCR0_ADDR
#define BN1_WF_AGG_TOP_MUCR0_MU_SPE_IDX_B0_MASK                0x001F0000                // MU_SPE_IDX_B0[20..16]
#define BN1_WF_AGG_TOP_MUCR0_MU_SPE_IDX_B0_SHFT                16
#define BN1_WF_AGG_TOP_MUCR0_MU_DYNBW_EN_B0_ADDR               BN1_WF_AGG_TOP_MUCR0_ADDR
#define BN1_WF_AGG_TOP_MUCR0_MU_DYNBW_EN_B0_MASK               0x00004000                // MU_DYNBW_EN_B0[14]
#define BN1_WF_AGG_TOP_MUCR0_MU_DYNBW_EN_B0_SHFT               14

/* =====================================================================================

  ---MUCR1 (0x820f2000 + 0xdc)---

    MU_ANT_ID_B0[23..0]          - (RW) MU antenna ID
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_MUCR1_MU_ANT_ID_B0_ADDR                 BN1_WF_AGG_TOP_MUCR1_ADDR
#define BN1_WF_AGG_TOP_MUCR1_MU_ANT_ID_B0_MASK                 0x00FFFFFF                // MU_ANT_ID_B0[23..0]
#define BN1_WF_AGG_TOP_MUCR1_MU_ANT_ID_B0_SHFT                 0

/* =====================================================================================

  ---MURDGCR0 (0x820f2000 + 0xe0)---

    MURDG_RDGR_DUR_B0[14..0]     - (RW) MURDG RDG reserved duration
                                     The duration granted to peer when MU RDG (1us). This duration is used when the chip is RDG initiator in MU.
    RESERVED15[15]               - (RO) Reserved bits
    MU_2ND_GUARD_DUR_B0[27..16]  - (RW) MU secondary guard duration from primary user (1us)
    RESERVED28[31..28]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_MURDGCR0_MU_2ND_GUARD_DUR_B0_ADDR       BN1_WF_AGG_TOP_MURDGCR0_ADDR
#define BN1_WF_AGG_TOP_MURDGCR0_MU_2ND_GUARD_DUR_B0_MASK       0x0FFF0000                // MU_2ND_GUARD_DUR_B0[27..16]
#define BN1_WF_AGG_TOP_MURDGCR0_MU_2ND_GUARD_DUR_B0_SHFT       16
#define BN1_WF_AGG_TOP_MURDGCR0_MURDG_RDGR_DUR_B0_ADDR         BN1_WF_AGG_TOP_MURDGCR0_ADDR
#define BN1_WF_AGG_TOP_MURDGCR0_MURDG_RDGR_DUR_B0_MASK         0x00007FFF                // MURDG_RDGR_DUR_B0[14..0]
#define BN1_WF_AGG_TOP_MURDGCR0_MURDG_RDGR_DUR_B0_SHFT         0

/* =====================================================================================

  ---MURDGCR1 (0x820f2000 + 0xe4)---

    MURDG_BAR_DUR_B0[9..0]       - (RW) BAR duration when MU RDG (1us)
                                     Should be the duration of BAR. This duration is used when the chip is RDG initiator in MU.
    RESERVED10[15..10]           - (RO) Reserved bits
    MURDG_BARBA_DUR_B0[25..16]   - (RW) BAR and BA duration when MU RDG (1us)
                                     Should be the duration of BAR + SIFS + BA + SIFS. This duration is used when the chip is RDG initiator in MU.
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_MURDGCR1_MURDG_BARBA_DUR_B0_ADDR        BN1_WF_AGG_TOP_MURDGCR1_ADDR
#define BN1_WF_AGG_TOP_MURDGCR1_MURDG_BARBA_DUR_B0_MASK        0x03FF0000                // MURDG_BARBA_DUR_B0[25..16]
#define BN1_WF_AGG_TOP_MURDGCR1_MURDG_BARBA_DUR_B0_SHFT        16
#define BN1_WF_AGG_TOP_MURDGCR1_MURDG_BAR_DUR_B0_ADDR          BN1_WF_AGG_TOP_MURDGCR1_ADDR
#define BN1_WF_AGG_TOP_MURDGCR1_MURDG_BAR_DUR_B0_MASK          0x000003FF                // MURDG_BAR_DUR_B0[9..0]
#define BN1_WF_AGG_TOP_MURDGCR1_MURDG_BAR_DUR_B0_SHFT          0

/* =====================================================================================

  ---CTCR (0x820f2000 + 0xe8)---

    RESERVED0[0]                 - (RO) Reserved bits
    TXOP_TXDLY_CTS[1]            - (RW) Issues CTS2Self to when retry happens within TXOP
                                     This CTS2Self can avoid unready cut-through data.
    CT_BW_CHG_EN[2]              - (RW) Enables cut-through bandwidth change
                                     If the air bandwidth condition changes at the last slot idle:
                                     1'b0: Abort this Tx
                                     1'b1: Change BW
                                     (Depending on BW change, the original PPDU length divides 2/4/8. If this new PPDU length is shorter than  the 1st packet, SU or MU primary will use the 1st packet length.)
    RESERVED3[13..3]             - (RO) Reserved bits
    DEQ_PROTECT_DIS[14]          - (RW) Dequeue Protection Disable. 
                                     0:Release MPDU count will not greater than TMAC MPDU count
                                     1:Release MPDU count might greater than TMAC MPDU count if receive a wrong BA Bitmap
    AGG_CNT_CT_EN[15]            - (RW) Enables AGG range counter (in MIB) involve cut-through
                                     For example, HW aggregates 32 MPDU. However cut-through leads to only transmitting 30 MPDU.
                                     If AGG_CNT_CT_EN=0, will get counter = 32.
                                     If AGG_CNT_CT_EN=1, will get counter = 30.
                                     MIB's AGG_RANG*_CNT
                                     MIB's AGG_MPDU_CNT
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_CTCR_AGG_CNT_CT_EN_ADDR                 BN1_WF_AGG_TOP_CTCR_ADDR
#define BN1_WF_AGG_TOP_CTCR_AGG_CNT_CT_EN_MASK                 0x00008000                // AGG_CNT_CT_EN[15]
#define BN1_WF_AGG_TOP_CTCR_AGG_CNT_CT_EN_SHFT                 15
#define BN1_WF_AGG_TOP_CTCR_DEQ_PROTECT_DIS_ADDR               BN1_WF_AGG_TOP_CTCR_ADDR
#define BN1_WF_AGG_TOP_CTCR_DEQ_PROTECT_DIS_MASK               0x00004000                // DEQ_PROTECT_DIS[14]
#define BN1_WF_AGG_TOP_CTCR_DEQ_PROTECT_DIS_SHFT               14
#define BN1_WF_AGG_TOP_CTCR_CT_BW_CHG_EN_ADDR                  BN1_WF_AGG_TOP_CTCR_ADDR
#define BN1_WF_AGG_TOP_CTCR_CT_BW_CHG_EN_MASK                  0x00000004                // CT_BW_CHG_EN[2]
#define BN1_WF_AGG_TOP_CTCR_CT_BW_CHG_EN_SHFT                  2
#define BN1_WF_AGG_TOP_CTCR_TXOP_TXDLY_CTS_ADDR                BN1_WF_AGG_TOP_CTCR_ADDR
#define BN1_WF_AGG_TOP_CTCR_TXOP_TXDLY_CTS_MASK                0x00000002                // TXOP_TXDLY_CTS[1]
#define BN1_WF_AGG_TOP_CTCR_TXOP_TXDLY_CTS_SHFT                1

/* =====================================================================================

  ---ATCR0 (0x820f2000 + 0xec)---

    MAX_BFF_TIME[19..0]          - (RW) Maximum back-off time limitation.
                                     (unit: 1.024us)
    RESERVED20[29..20]           - (RO) Reserved bits
    MAX_BFF_TIME_EN[30]          - (RW) Maximum back-off time limit enable.
                                     0: no limitation
                                     1: if back-off time > MAX_BFF_TIME, use MAX_BFF_TIME for air time fairness
    BFF_TIME_OVER_MAX_STS[31]    - (W1C) Indicated back-off time was ever over MAX_BFF_TIME or not.

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ATCR0_BFF_TIME_OVER_MAX_STS_ADDR        BN1_WF_AGG_TOP_ATCR0_ADDR
#define BN1_WF_AGG_TOP_ATCR0_BFF_TIME_OVER_MAX_STS_MASK        0x80000000                // BFF_TIME_OVER_MAX_STS[31]
#define BN1_WF_AGG_TOP_ATCR0_BFF_TIME_OVER_MAX_STS_SHFT        31
#define BN1_WF_AGG_TOP_ATCR0_MAX_BFF_TIME_EN_ADDR              BN1_WF_AGG_TOP_ATCR0_ADDR
#define BN1_WF_AGG_TOP_ATCR0_MAX_BFF_TIME_EN_MASK              0x40000000                // MAX_BFF_TIME_EN[30]
#define BN1_WF_AGG_TOP_ATCR0_MAX_BFF_TIME_EN_SHFT              30
#define BN1_WF_AGG_TOP_ATCR0_MAX_BFF_TIME_ADDR                 BN1_WF_AGG_TOP_ATCR0_ADDR
#define BN1_WF_AGG_TOP_ATCR0_MAX_BFF_TIME_MASK                 0x000FFFFF                // MAX_BFF_TIME[19..0]
#define BN1_WF_AGG_TOP_ATCR0_MAX_BFF_TIME_SHFT                 0

/* =====================================================================================

  ---ATCR1 (0x820f2000 + 0xf0)---

    RTS_FAIL_CHARGE_DIS[0]       - (RW) When protect by RTS but receive CTS fail, charge air time or not.
                                     0: charge RTS/CTS time
                                     1: don't charge RTS/CTS time (original design)
    RTS_FAIL_PKT_DROP_CHARGE_CHARGE_EN[1] - (RW) Enable to charge time when packet dropped due to RTS fail reach limit.
    RESERVED2[15..2]             - (RO) Reserved bits
    RTS_FAIL_PKT_DROP_CHARGE_CHARGE_TIME[31..16] - (RW) Charge time of airtime report when packet dropped due to RTS fail reach limit.

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ATCR1_RTS_FAIL_PKT_DROP_CHARGE_CHARGE_TIME_ADDR BN1_WF_AGG_TOP_ATCR1_ADDR
#define BN1_WF_AGG_TOP_ATCR1_RTS_FAIL_PKT_DROP_CHARGE_CHARGE_TIME_MASK 0xFFFF0000                // RTS_FAIL_PKT_DROP_CHARGE_CHARGE_TIME[31..16]
#define BN1_WF_AGG_TOP_ATCR1_RTS_FAIL_PKT_DROP_CHARGE_CHARGE_TIME_SHFT 16
#define BN1_WF_AGG_TOP_ATCR1_RTS_FAIL_PKT_DROP_CHARGE_CHARGE_EN_ADDR BN1_WF_AGG_TOP_ATCR1_ADDR
#define BN1_WF_AGG_TOP_ATCR1_RTS_FAIL_PKT_DROP_CHARGE_CHARGE_EN_MASK 0x00000002                // RTS_FAIL_PKT_DROP_CHARGE_CHARGE_EN[1]
#define BN1_WF_AGG_TOP_ATCR1_RTS_FAIL_PKT_DROP_CHARGE_CHARGE_EN_SHFT 1
#define BN1_WF_AGG_TOP_ATCR1_RTS_FAIL_CHARGE_DIS_ADDR          BN1_WF_AGG_TOP_ATCR1_ADDR
#define BN1_WF_AGG_TOP_ATCR1_RTS_FAIL_CHARGE_DIS_MASK          0x00000001                // RTS_FAIL_CHARGE_DIS[0]
#define BN1_WF_AGG_TOP_ATCR1_RTS_FAIL_CHARGE_DIS_SHFT          0

/* =====================================================================================

  ---ATCR3 (0x820f2000 + 0xf4)---

    LOCK_DRR_EN_B0[0]            - (RW) LOCK DRR Enable. Lock DRR when RTS fial to provent UMAC change peer.
                                     0: Disable
                                     1: Enable
    STA_MPDU_FAIL_LOCK_EN_B0[1]  - (RW) STA MPDU FAIL LOCK Enable for Band0. Lock DRR when STA MPDU fial to provent UMAC change peer.
                                     0: Disable
                                     1: Enable
    RESERVED2[31..2]             - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_ATCR3_STA_MPDU_FAIL_LOCK_EN_B0_ADDR     BN1_WF_AGG_TOP_ATCR3_ADDR
#define BN1_WF_AGG_TOP_ATCR3_STA_MPDU_FAIL_LOCK_EN_B0_MASK     0x00000002                // STA_MPDU_FAIL_LOCK_EN_B0[1]
#define BN1_WF_AGG_TOP_ATCR3_STA_MPDU_FAIL_LOCK_EN_B0_SHFT     1
#define BN1_WF_AGG_TOP_ATCR3_LOCK_DRR_EN_B0_ADDR               BN1_WF_AGG_TOP_ATCR3_ADDR
#define BN1_WF_AGG_TOP_ATCR3_LOCK_DRR_EN_B0_MASK               0x00000001                // LOCK_DRR_EN_B0[0]
#define BN1_WF_AGG_TOP_ATCR3_LOCK_DRR_EN_B0_SHFT               0

/* =====================================================================================

  ---SRCR (0x820f2000 + 0xf8)---

    SR_REM_TIME_EN[0]            - (RW) Indicate to use Spatial Reuse Remainning Time to constraint PPDU time during spatial reuse window.(RESERVE CR)
                                     0: Disable
                                     1: Enable
    RESERVED1[31..1]             - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_SRCR_SR_REM_TIME_EN_ADDR                BN1_WF_AGG_TOP_SRCR_ADDR
#define BN1_WF_AGG_TOP_SRCR_SR_REM_TIME_EN_MASK                0x00000001                // SR_REM_TIME_EN[0]
#define BN1_WF_AGG_TOP_SRCR_SR_REM_TIME_EN_SHFT                0

/* =====================================================================================

  ---VBCR (0x820f2000 + 0xfc)---

    ADM_BYTE_CNT_INCLUDE_MGNT[0] - (RW) Admission Control Byte Counter include management frame type
                                     0: not include
                                     1: inlcude
    RESERVED1[31..1]             - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_VBCR_ADM_BYTE_CNT_INCLUDE_MGNT_ADDR     BN1_WF_AGG_TOP_VBCR_ADDR
#define BN1_WF_AGG_TOP_VBCR_ADM_BYTE_CNT_INCLUDE_MGNT_MASK     0x00000001                // ADM_BYTE_CNT_INCLUDE_MGNT[0]
#define BN1_WF_AGG_TOP_VBCR_ADM_BYTE_CNT_INCLUDE_MGNT_SHFT     0

/* =====================================================================================

  ---B0BRR0 (0x820f2000 + 0x100)---

    BN0_BSSID00_LG_RATE_MAP[11..0] - (RW) Primary rate bitmap for BAND0 BSSID00/BSSID1x/BSSID2x (ACK/BA/MTBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[3:0]: CCK 11/5.5/2/1M
                                     Bit[11:4]: OFDM 54/48/36/24/18/12/9/6M
                                     (For BAND 0 TX/RX)
    RESERVED12[31..12]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_B0BRR0_BN0_BSSID00_LG_RATE_MAP_ADDR     BN1_WF_AGG_TOP_B0BRR0_ADDR
#define BN1_WF_AGG_TOP_B0BRR0_BN0_BSSID00_LG_RATE_MAP_MASK     0x00000FFF                // BN0_BSSID00_LG_RATE_MAP[11..0]
#define BN1_WF_AGG_TOP_B0BRR0_BN0_BSSID00_LG_RATE_MAP_SHFT     0

/* =====================================================================================

  ---B1BRR0 (0x820f2000 + 0x104)---

    BSSID01_LG_RATE_MAP[11..0]   - (RW) Primary rate bitmap for BSSID01 (ACK/BA/MTBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[3:0]: CCK 11/5.5/2/1M
                                     Bit[11:4]: OFDM 54/48/36/24/18/12/9/6M
    RESERVED12[31..12]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_B1BRR0_BSSID01_LG_RATE_MAP_ADDR         BN1_WF_AGG_TOP_B1BRR0_ADDR
#define BN1_WF_AGG_TOP_B1BRR0_BSSID01_LG_RATE_MAP_MASK         0x00000FFF                // BSSID01_LG_RATE_MAP[11..0]
#define BN1_WF_AGG_TOP_B1BRR0_BSSID01_LG_RATE_MAP_SHFT         0

/* =====================================================================================

  ---B2BRR0 (0x820f2000 + 0x108)---

    BSSID02_LG_RATE_MAP[11..0]   - (RW) Primary rate bitmap for BSSID02 (ACK/BA/MTBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[3:0]: CCK 11/5.5/2/1M
                                     Bit[11:4]: OFDM 54/48/36/24/18/12/9/6M
    RESERVED12[31..12]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_B2BRR0_BSSID02_LG_RATE_MAP_ADDR         BN1_WF_AGG_TOP_B2BRR0_ADDR
#define BN1_WF_AGG_TOP_B2BRR0_BSSID02_LG_RATE_MAP_MASK         0x00000FFF                // BSSID02_LG_RATE_MAP[11..0]
#define BN1_WF_AGG_TOP_B2BRR0_BSSID02_LG_RATE_MAP_SHFT         0

/* =====================================================================================

  ---B3BRR0 (0x820f2000 + 0x10c)---

    BSSID03_LG_RATE_MAP[11..0]   - (RW) Primary rate bitmap for BSSID03 (ACK/BA/MTBA/CTS)
                                     1'b0: Not support
                                     1'b1: Support
                                     Bit[3:0]: CCK 11/5.5/2/1M
                                     Bit[11:4]: OFDM 54/48/36/24/18/12/9/6M
    RESERVED12[31..12]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_B3BRR0_BSSID03_LG_RATE_MAP_ADDR         BN1_WF_AGG_TOP_B3BRR0_ADDR
#define BN1_WF_AGG_TOP_B3BRR0_BSSID03_LG_RATE_MAP_MASK         0x00000FFF                // BSSID03_LG_RATE_MAP[11..0]
#define BN1_WF_AGG_TOP_B3BRR0_BSSID03_LG_RATE_MAP_SHFT         0

/* =====================================================================================

  ---TWTCR (0x820f2000 + 0x110)---

    TWTTXCTRL[0]                 - (RW) TWT Transmission Control 
                                     0: Whole PPDU should be within SP referred from twtSpTblidx 
                                     1: The start time of PPDU within SP while the end time could exceed the end of SP
    RESERVED1[31..1]             - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTCR_TWTTXCTRL_ADDR                    BN1_WF_AGG_TOP_TWTCR_ADDR
#define BN1_WF_AGG_TOP_TWTCR_TWTTXCTRL_MASK                    0x00000001                // TWTTXCTRL[0]
#define BN1_WF_AGG_TOP_TWTCR_TWTTXCTRL_SHFT                    0

/* =====================================================================================

  ---TWTSTACR (0x820f2000 + 0x114)---

    TWTSTA_TBLIDX0[3..0]         - (RW) Present Service Period Index for BSSID0;  Use this field to identify Present SP duration calculated by SW and stored in TWT Present Service Period Table
    RESERVED4[6..4]              - (RO) Reserved bits
    TWTSTA_VALID0[7]             - (RW) TWT STA MODE VALID for BSSID0
                                     0: False
                                     1: True
    TWTSTA_TBLIDX1[11..8]        - (RW) Present Service Period Index for BSSID1;  Use this field to identify Present SP duration calculated by SW and stored in TWT Present Service Period Table
    RESERVED12[14..12]           - (RO) Reserved bits
    TWTSTA_VALID1[15]            - (RW) TWT STA MODE VALID for BSSID1
                                     0: False
                                     1: True
    TWTSTA_TBLIDX2[19..16]       - (RW) Present Service Period Index for BSSID2;  Use this field to identify Present SP duration calculated by SW and stored in TWT Present Service Period Table
    RESERVED20[22..20]           - (RO) Reserved bits
    TWTSTA_VALID2[23]            - (RW) TWT STA MODE VALID for BSSID2
                                     0: False
                                     1: True
    TWTSTA_TBLIDX3[27..24]       - (RW) Present Service Period Index for BSSID3;  Use this field to identify Present SP duration calculated by SW and stored in TWT Present Service Period Table
    RESERVED28[30..28]           - (RO) Reserved bits
    TWTSTA_VALID3[31]            - (RW) TWT STA MODE VALID for BSSID3
                                     0: False
                                     1: True

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_VALID3_ADDR             BN1_WF_AGG_TOP_TWTSTACR_ADDR
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_VALID3_MASK             0x80000000                // TWTSTA_VALID3[31]
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_VALID3_SHFT             31
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_TBLIDX3_ADDR            BN1_WF_AGG_TOP_TWTSTACR_ADDR
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_TBLIDX3_MASK            0x0F000000                // TWTSTA_TBLIDX3[27..24]
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_TBLIDX3_SHFT            24
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_VALID2_ADDR             BN1_WF_AGG_TOP_TWTSTACR_ADDR
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_VALID2_MASK             0x00800000                // TWTSTA_VALID2[23]
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_VALID2_SHFT             23
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_TBLIDX2_ADDR            BN1_WF_AGG_TOP_TWTSTACR_ADDR
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_TBLIDX2_MASK            0x000F0000                // TWTSTA_TBLIDX2[19..16]
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_TBLIDX2_SHFT            16
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_VALID1_ADDR             BN1_WF_AGG_TOP_TWTSTACR_ADDR
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_VALID1_MASK             0x00008000                // TWTSTA_VALID1[15]
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_VALID1_SHFT             15
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_TBLIDX1_ADDR            BN1_WF_AGG_TOP_TWTSTACR_ADDR
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_TBLIDX1_MASK            0x00000F00                // TWTSTA_TBLIDX1[11..8]
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_TBLIDX1_SHFT            8
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_VALID0_ADDR             BN1_WF_AGG_TOP_TWTSTACR_ADDR
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_VALID0_MASK             0x00000080                // TWTSTA_VALID0[7]
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_VALID0_SHFT             7
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_TBLIDX0_ADDR            BN1_WF_AGG_TOP_TWTSTACR_ADDR
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_TBLIDX0_MASK            0x0000000F                // TWTSTA_TBLIDX0[3..0]
#define BN1_WF_AGG_TOP_TWTSTACR_TWTSTA_TBLIDX0_SHFT            0

/* =====================================================================================

  ---TWTE0TB (0x820f2000 + 0x118)---

    TWTE0TB1_START_TSF[19..0]    - (RW) TWT Entry0 Table Present SP Start TSF time
    TWTE0TB1_END_TSF[31..20]     - (RW) TWT Entry0 Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTE0TB_TWTE0TB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTE0TB_ADDR
#define BN1_WF_AGG_TOP_TWTE0TB_TWTE0TB1_END_TSF_MASK           0xFFF00000                // TWTE0TB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTE0TB_TWTE0TB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTE0TB_TWTE0TB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTE0TB_ADDR
#define BN1_WF_AGG_TOP_TWTE0TB_TWTE0TB1_START_TSF_MASK         0x000FFFFF                // TWTE0TB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTE0TB_TWTE0TB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTE1TB (0x820f2000 + 0x11c)---

    TWTE1TB1_START_TSF[19..0]    - (RW) TWT Entry1 Table Present SP Start TSF time
    TWTE1TB1_END_TSF[31..20]     - (RW) TWT Entry1 Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTE1TB_TWTE1TB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTE1TB_ADDR
#define BN1_WF_AGG_TOP_TWTE1TB_TWTE1TB1_END_TSF_MASK           0xFFF00000                // TWTE1TB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTE1TB_TWTE1TB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTE1TB_TWTE1TB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTE1TB_ADDR
#define BN1_WF_AGG_TOP_TWTE1TB_TWTE1TB1_START_TSF_MASK         0x000FFFFF                // TWTE1TB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTE1TB_TWTE1TB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTE2TB (0x820f2000 + 0x120)---

    TWTE2TB1_START_TSF[19..0]    - (RW) TWT Entry2 Table Present SP Start TSF time
    TWTE2TB1_END_TSF[31..20]     - (RW) TWT Entry2 Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTE2TB_TWTE2TB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTE2TB_ADDR
#define BN1_WF_AGG_TOP_TWTE2TB_TWTE2TB1_END_TSF_MASK           0xFFF00000                // TWTE2TB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTE2TB_TWTE2TB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTE2TB_TWTE2TB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTE2TB_ADDR
#define BN1_WF_AGG_TOP_TWTE2TB_TWTE2TB1_START_TSF_MASK         0x000FFFFF                // TWTE2TB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTE2TB_TWTE2TB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTE3TB (0x820f2000 + 0x124)---

    TWTE3TB1_START_TSF[19..0]    - (RW) TWT Entry3 Table Present SP Start TSF time
    TWTE3TB1_END_TSF[31..20]     - (RW) TWT Entry3 Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTE3TB_TWTE3TB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTE3TB_ADDR
#define BN1_WF_AGG_TOP_TWTE3TB_TWTE3TB1_END_TSF_MASK           0xFFF00000                // TWTE3TB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTE3TB_TWTE3TB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTE3TB_TWTE3TB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTE3TB_ADDR
#define BN1_WF_AGG_TOP_TWTE3TB_TWTE3TB1_START_TSF_MASK         0x000FFFFF                // TWTE3TB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTE3TB_TWTE3TB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTE4TB (0x820f2000 + 0x128)---

    TWTE4TB1_START_TSF[19..0]    - (RW) TWT Entry4 Table Present SP Start TSF time
    TWTE4TB1_END_TSF[31..20]     - (RW) TWT Entry4 Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTE4TB_TWTE4TB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTE4TB_ADDR
#define BN1_WF_AGG_TOP_TWTE4TB_TWTE4TB1_END_TSF_MASK           0xFFF00000                // TWTE4TB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTE4TB_TWTE4TB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTE4TB_TWTE4TB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTE4TB_ADDR
#define BN1_WF_AGG_TOP_TWTE4TB_TWTE4TB1_START_TSF_MASK         0x000FFFFF                // TWTE4TB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTE4TB_TWTE4TB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTE5TB (0x820f2000 + 0x12c)---

    TWTE5TB1_START_TSF[19..0]    - (RW) TWT Entry5 Table Present SP Start TSF time
    TWTE5TB1_END_TSF[31..20]     - (RW) TWT Entry5 Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTE5TB_TWTE5TB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTE5TB_ADDR
#define BN1_WF_AGG_TOP_TWTE5TB_TWTE5TB1_END_TSF_MASK           0xFFF00000                // TWTE5TB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTE5TB_TWTE5TB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTE5TB_TWTE5TB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTE5TB_ADDR
#define BN1_WF_AGG_TOP_TWTE5TB_TWTE5TB1_START_TSF_MASK         0x000FFFFF                // TWTE5TB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTE5TB_TWTE5TB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTE6TB (0x820f2000 + 0x130)---

    TWTE6TB1_START_TSF[19..0]    - (RW) TWT Entry6 Table Present SP Start TSF time
    TWTE6TB1_END_TSF[31..20]     - (RW) TWT Entry6 Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTE6TB_TWTE6TB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTE6TB_ADDR
#define BN1_WF_AGG_TOP_TWTE6TB_TWTE6TB1_END_TSF_MASK           0xFFF00000                // TWTE6TB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTE6TB_TWTE6TB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTE6TB_TWTE6TB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTE6TB_ADDR
#define BN1_WF_AGG_TOP_TWTE6TB_TWTE6TB1_START_TSF_MASK         0x000FFFFF                // TWTE6TB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTE6TB_TWTE6TB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTE7TB (0x820f2000 + 0x134)---

    TWTE7TB1_START_TSF[19..0]    - (RW) TWT Entry7 Table Present SP Start TSF time
    TWTE7TB1_END_TSF[31..20]     - (RW) TWT Entry7 Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTE7TB_TWTE7TB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTE7TB_ADDR
#define BN1_WF_AGG_TOP_TWTE7TB_TWTE7TB1_END_TSF_MASK           0xFFF00000                // TWTE7TB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTE7TB_TWTE7TB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTE7TB_TWTE7TB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTE7TB_ADDR
#define BN1_WF_AGG_TOP_TWTE7TB_TWTE7TB1_START_TSF_MASK         0x000FFFFF                // TWTE7TB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTE7TB_TWTE7TB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTE8TB (0x820f2000 + 0x138)---

    TWTE8TB1_START_TSF[19..0]    - (RW) TWT Entry8 Table Present SP Start TSF time
    TWTE8TB1_END_TSF[31..20]     - (RW) TWT Entry8 Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTE8TB_TWTE8TB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTE8TB_ADDR
#define BN1_WF_AGG_TOP_TWTE8TB_TWTE8TB1_END_TSF_MASK           0xFFF00000                // TWTE8TB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTE8TB_TWTE8TB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTE8TB_TWTE8TB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTE8TB_ADDR
#define BN1_WF_AGG_TOP_TWTE8TB_TWTE8TB1_START_TSF_MASK         0x000FFFFF                // TWTE8TB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTE8TB_TWTE8TB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTE9TB (0x820f2000 + 0x13c)---

    TWTE9TB1_START_TSF[19..0]    - (RW) TWT Entry9 Table Present SP Start TSF time
    TWTE9TB1_END_TSF[31..20]     - (RW) TWT Entry9 Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTE9TB_TWTE9TB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTE9TB_ADDR
#define BN1_WF_AGG_TOP_TWTE9TB_TWTE9TB1_END_TSF_MASK           0xFFF00000                // TWTE9TB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTE9TB_TWTE9TB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTE9TB_TWTE9TB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTE9TB_ADDR
#define BN1_WF_AGG_TOP_TWTE9TB_TWTE9TB1_START_TSF_MASK         0x000FFFFF                // TWTE9TB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTE9TB_TWTE9TB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTEATB (0x820f2000 + 0x140)---

    TWTEATB1_START_TSF[19..0]    - (RW) TWT EntryA Table Present SP Start TSF time
    TWTEATB1_END_TSF[31..20]     - (RW) TWT EntryA Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTEATB_TWTEATB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTEATB_ADDR
#define BN1_WF_AGG_TOP_TWTEATB_TWTEATB1_END_TSF_MASK           0xFFF00000                // TWTEATB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTEATB_TWTEATB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTEATB_TWTEATB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTEATB_ADDR
#define BN1_WF_AGG_TOP_TWTEATB_TWTEATB1_START_TSF_MASK         0x000FFFFF                // TWTEATB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTEATB_TWTEATB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTEBTB (0x820f2000 + 0x144)---

    TWTEBTB1_START_TSF[19..0]    - (RW) TWT EntryB Table Present SP Start TSF time
    TWTEBTB1_END_TSF[31..20]     - (RW) TWT EntryB Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTEBTB_TWTEBTB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTEBTB_ADDR
#define BN1_WF_AGG_TOP_TWTEBTB_TWTEBTB1_END_TSF_MASK           0xFFF00000                // TWTEBTB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTEBTB_TWTEBTB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTEBTB_TWTEBTB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTEBTB_ADDR
#define BN1_WF_AGG_TOP_TWTEBTB_TWTEBTB1_START_TSF_MASK         0x000FFFFF                // TWTEBTB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTEBTB_TWTEBTB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTECTB (0x820f2000 + 0x148)---

    TWTECTB1_START_TSF[19..0]    - (RW) TWT EntryC Table Present SP Start TSF time
    TWTECTB1_END_TSF[31..20]     - (RW) TWT EntryC Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTECTB_TWTECTB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTECTB_ADDR
#define BN1_WF_AGG_TOP_TWTECTB_TWTECTB1_END_TSF_MASK           0xFFF00000                // TWTECTB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTECTB_TWTECTB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTECTB_TWTECTB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTECTB_ADDR
#define BN1_WF_AGG_TOP_TWTECTB_TWTECTB1_START_TSF_MASK         0x000FFFFF                // TWTECTB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTECTB_TWTECTB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTEDTB (0x820f2000 + 0x14c)---

    TWTEDTB1_START_TSF[19..0]    - (RW) TWT EntryD Table Present SP Start TSF time
    TWTEDTB1_END_TSF[31..20]     - (RW) TWT EntryD Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTEDTB_TWTEDTB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTEDTB_ADDR
#define BN1_WF_AGG_TOP_TWTEDTB_TWTEDTB1_END_TSF_MASK           0xFFF00000                // TWTEDTB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTEDTB_TWTEDTB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTEDTB_TWTEDTB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTEDTB_ADDR
#define BN1_WF_AGG_TOP_TWTEDTB_TWTEDTB1_START_TSF_MASK         0x000FFFFF                // TWTEDTB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTEDTB_TWTEDTB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTEETB (0x820f2000 + 0x150)---

    TWTEETB1_START_TSF[19..0]    - (RW) TWT EntryE Table Present SP Start TSF time
    TWTEETB1_END_TSF[31..20]     - (RW) TWT EntryE Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTEETB_TWTEETB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTEETB_ADDR
#define BN1_WF_AGG_TOP_TWTEETB_TWTEETB1_END_TSF_MASK           0xFFF00000                // TWTEETB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTEETB_TWTEETB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTEETB_TWTEETB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTEETB_ADDR
#define BN1_WF_AGG_TOP_TWTEETB_TWTEETB1_START_TSF_MASK         0x000FFFFF                // TWTEETB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTEETB_TWTEETB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TWTEFTB (0x820f2000 + 0x154)---

    TWTEFTB1_START_TSF[19..0]    - (RW) TWT EntryF Table Present SP Start TSF time
    TWTEFTB1_END_TSF[31..20]     - (RW) TWT EntryF Table Present SP Shelf TSF time: SP End time should be {END_TSF,START_TSF[7:0]}

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TWTEFTB_TWTEFTB1_END_TSF_ADDR           BN1_WF_AGG_TOP_TWTEFTB_ADDR
#define BN1_WF_AGG_TOP_TWTEFTB_TWTEFTB1_END_TSF_MASK           0xFFF00000                // TWTEFTB1_END_TSF[31..20]
#define BN1_WF_AGG_TOP_TWTEFTB_TWTEFTB1_END_TSF_SHFT           20
#define BN1_WF_AGG_TOP_TWTEFTB_TWTEFTB1_START_TSF_ADDR         BN1_WF_AGG_TOP_TWTEFTB_ADDR
#define BN1_WF_AGG_TOP_TWTEFTB_TWTEFTB1_START_TSF_MASK         0x000FFFFF                // TWTEFTB1_START_TSF[19..0]
#define BN1_WF_AGG_TOP_TWTEFTB_TWTEFTB1_START_TSF_SHFT         0

/* =====================================================================================

  ---TCR (0x820f2000 + 0x158)---

    REM_TXOP_THRESHOLD[3..0]     - (RW) Unit is 16 us. If TMAC remaining TXOP > this threshold, allow to continue TX.
    RESERVED4[31..4]             - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TCR_REM_TXOP_THRESHOLD_ADDR             BN1_WF_AGG_TOP_TCR_ADDR
#define BN1_WF_AGG_TOP_TCR_REM_TXOP_THRESHOLD_MASK             0x0000000F                // REM_TXOP_THRESHOLD[3..0]
#define BN1_WF_AGG_TOP_TCR_REM_TXOP_THRESHOLD_SHFT             0

/* =====================================================================================

  ---DBRCR0 (0x820f2000 + 0x15c)---

    DUR_BASED_RTS_THRESHOLD_OM_0[9..0] - (RW) Duration Based RTS Threshold for OM 0
                                     If PPDU tx time is larger than this threshold, the RTS/CTS frame will be required.(unit is us)
    RESERVED10[15..10]           - (RO) Reserved bits
    DUR_BASED_RTS_THRESHOLD_OM_1[25..16] - (RW) Duration Based RTS Threshold for OM 1
                                     If PPDU tx time is larger than this threshold, the RTS/CTS frame will be required.(unit is us)
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_DBRCR0_DUR_BASED_RTS_THRESHOLD_OM_1_ADDR BN1_WF_AGG_TOP_DBRCR0_ADDR
#define BN1_WF_AGG_TOP_DBRCR0_DUR_BASED_RTS_THRESHOLD_OM_1_MASK 0x03FF0000                // DUR_BASED_RTS_THRESHOLD_OM_1[25..16]
#define BN1_WF_AGG_TOP_DBRCR0_DUR_BASED_RTS_THRESHOLD_OM_1_SHFT 16
#define BN1_WF_AGG_TOP_DBRCR0_DUR_BASED_RTS_THRESHOLD_OM_0_ADDR BN1_WF_AGG_TOP_DBRCR0_ADDR
#define BN1_WF_AGG_TOP_DBRCR0_DUR_BASED_RTS_THRESHOLD_OM_0_MASK 0x000003FF                // DUR_BASED_RTS_THRESHOLD_OM_0[9..0]
#define BN1_WF_AGG_TOP_DBRCR0_DUR_BASED_RTS_THRESHOLD_OM_0_SHFT 0

/* =====================================================================================

  ---DBRCR1 (0x820f2000 + 0x160)---

    DUR_BASED_RTS_THRESHOLD_OM_2[9..0] - (RW) Duration Based RTS Threshold for OM 2
                                     If PPDU tx time is larger than this threshold, the RTS/CTS frame will be required.(unit is us)
    RESERVED10[15..10]           - (RO) Reserved bits
    DUR_BASED_RTS_THRESHOLD_OM_3[25..16] - (RW) Duration Based RTS Threshold for OM 3
                                     If PPDU tx time is larger than this threshold, the RTS/CTS frame will be required.(unit is us)
    RESERVED26[31..26]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_DBRCR1_DUR_BASED_RTS_THRESHOLD_OM_3_ADDR BN1_WF_AGG_TOP_DBRCR1_ADDR
#define BN1_WF_AGG_TOP_DBRCR1_DUR_BASED_RTS_THRESHOLD_OM_3_MASK 0x03FF0000                // DUR_BASED_RTS_THRESHOLD_OM_3[25..16]
#define BN1_WF_AGG_TOP_DBRCR1_DUR_BASED_RTS_THRESHOLD_OM_3_SHFT 16
#define BN1_WF_AGG_TOP_DBRCR1_DUR_BASED_RTS_THRESHOLD_OM_2_ADDR BN1_WF_AGG_TOP_DBRCR1_ADDR
#define BN1_WF_AGG_TOP_DBRCR1_DUR_BASED_RTS_THRESHOLD_OM_2_MASK 0x000003FF                // DUR_BASED_RTS_THRESHOLD_OM_2[9..0]
#define BN1_WF_AGG_TOP_DBRCR1_DUR_BASED_RTS_THRESHOLD_OM_2_SHFT 0

/* =====================================================================================

  ---SRHS (0x820f2000 + 0x164)---

    SMALL_RU_SIZE_OM0_AC[1..0]   - (RW) Indicate which AC of OM0 has small ru size issue; Vlaid when SMALL_RU_SIZE_OM0_AC_VLD is high;
    RESERVED2[6..2]              - (RO) Reserved bits
    SMALL_RU_SIZE_OM0_AC_VLD[7]  - (RW) Valid indicator for SMALL_RU_SIZE_OM0_AC; HW set 1 when RU size of trigger frame is too small for OM0; SW set 0 to clear;
    SMALL_RU_SIZE_OM1_AC[9..8]   - (RW) Indicate which AC of OM1 has small ru size issue; Vlaid when SMALL_RU_SIZE_OM1_AC_VLD is high;
    RESERVED10[14..10]           - (RO) Reserved bits
    SMALL_RU_SIZE_OM1_AC_VLD[15] - (RW) Valid indicator for SMALL_RU_SIZE_OM1_AC; HW set 1 when RU size of trigger frame is too small for OM1; SW set 0 to clear;
    SMALL_RU_SIZE_OM2_AC[16]     - (RW) Indicate which AC of OM2 has small ru size issue; Vlaid when SMALL_RU_SIZE_OM2_AC_VLD is high;
    RESERVED17[22..17]           - (RO) Reserved bits
    SMALL_RU_SIZE_OM2_AC_VLD[23] - (RW) Valid indicator for SMALL_RU_SIZE_OM2_AC; HW set 1 when RU size of trigger frame is too small for OM2; SW set 0 to clear;
    SMALL_RU_SIZE_OM3_AC[25..24] - (RW) Indicate which AC of OM3 has small ru size issue; Vlaid when SMALL_RU_SIZE_OM3_AC_VLD is high;
    RESERVED26[30..26]           - (RO) Reserved bits
    SMALL_RU_SIZE_OM3_AC_VLD[31] - (RW) Valid indicator for SMALL_RU_SIZE_OM3_AC; HW set 1 when RU size of trigger frame is too small for OM3; SW set 0 to clear;

 =====================================================================================*/
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM3_AC_VLD_ADDR      BN1_WF_AGG_TOP_SRHS_ADDR
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM3_AC_VLD_MASK      0x80000000                // SMALL_RU_SIZE_OM3_AC_VLD[31]
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM3_AC_VLD_SHFT      31
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM3_AC_ADDR          BN1_WF_AGG_TOP_SRHS_ADDR
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM3_AC_MASK          0x03000000                // SMALL_RU_SIZE_OM3_AC[25..24]
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM3_AC_SHFT          24
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM2_AC_VLD_ADDR      BN1_WF_AGG_TOP_SRHS_ADDR
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM2_AC_VLD_MASK      0x00800000                // SMALL_RU_SIZE_OM2_AC_VLD[23]
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM2_AC_VLD_SHFT      23
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM2_AC_ADDR          BN1_WF_AGG_TOP_SRHS_ADDR
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM2_AC_MASK          0x00010000                // SMALL_RU_SIZE_OM2_AC[16]
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM2_AC_SHFT          16
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM1_AC_VLD_ADDR      BN1_WF_AGG_TOP_SRHS_ADDR
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM1_AC_VLD_MASK      0x00008000                // SMALL_RU_SIZE_OM1_AC_VLD[15]
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM1_AC_VLD_SHFT      15
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM1_AC_ADDR          BN1_WF_AGG_TOP_SRHS_ADDR
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM1_AC_MASK          0x00000300                // SMALL_RU_SIZE_OM1_AC[9..8]
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM1_AC_SHFT          8
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM0_AC_VLD_ADDR      BN1_WF_AGG_TOP_SRHS_ADDR
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM0_AC_VLD_MASK      0x00000080                // SMALL_RU_SIZE_OM0_AC_VLD[7]
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM0_AC_VLD_SHFT      7
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM0_AC_ADDR          BN1_WF_AGG_TOP_SRHS_ADDR
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM0_AC_MASK          0x00000003                // SMALL_RU_SIZE_OM0_AC[1..0]
#define BN1_WF_AGG_TOP_SRHS_SMALL_RU_SIZE_OM0_AC_SHFT          0

/* =====================================================================================

  ---TCSR0 (0x820f2000 + 0x168)---

    HW_BASIC_TRIG_CNT[7..0]      - (RO) HW Basic Trigger Frame Counter
    SW_BASIC_TRIG_CNT[15..8]     - (RO) HW Basic Trigger Frame Counter
    SW_BRP_TRIG_CNT[23..16]      - (RO) SW Beamforming Report Poll Trigger Frame Counter
    HW_MUBAR_TRIG_CNT[31..24]    - (RO) HW MU BAR Trigger Frame Counter

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TCSR0_HW_MUBAR_TRIG_CNT_ADDR            BN1_WF_AGG_TOP_TCSR0_ADDR
#define BN1_WF_AGG_TOP_TCSR0_HW_MUBAR_TRIG_CNT_MASK            0xFF000000                // HW_MUBAR_TRIG_CNT[31..24]
#define BN1_WF_AGG_TOP_TCSR0_HW_MUBAR_TRIG_CNT_SHFT            24
#define BN1_WF_AGG_TOP_TCSR0_SW_BRP_TRIG_CNT_ADDR              BN1_WF_AGG_TOP_TCSR0_ADDR
#define BN1_WF_AGG_TOP_TCSR0_SW_BRP_TRIG_CNT_MASK              0x00FF0000                // SW_BRP_TRIG_CNT[23..16]
#define BN1_WF_AGG_TOP_TCSR0_SW_BRP_TRIG_CNT_SHFT              16
#define BN1_WF_AGG_TOP_TCSR0_SW_BASIC_TRIG_CNT_ADDR            BN1_WF_AGG_TOP_TCSR0_ADDR
#define BN1_WF_AGG_TOP_TCSR0_SW_BASIC_TRIG_CNT_MASK            0x0000FF00                // SW_BASIC_TRIG_CNT[15..8]
#define BN1_WF_AGG_TOP_TCSR0_SW_BASIC_TRIG_CNT_SHFT            8
#define BN1_WF_AGG_TOP_TCSR0_HW_BASIC_TRIG_CNT_ADDR            BN1_WF_AGG_TOP_TCSR0_ADDR
#define BN1_WF_AGG_TOP_TCSR0_HW_BASIC_TRIG_CNT_MASK            0x000000FF                // HW_BASIC_TRIG_CNT[7..0]
#define BN1_WF_AGG_TOP_TCSR0_HW_BASIC_TRIG_CNT_SHFT            0

/* =====================================================================================

  ---TCSR1 (0x820f2000 + 0x16c)---

    HW_MURTS_TRIG_CNT[7..0]      - (RO) HW MU RTS Trigger Frame Counter
    SW_BSRP_TRIG_CNT[15..8]      - (RO) HW Buffer Status Report Poll Trigger Frame Counter
    SW_GCRMUBAR_TRIG_CNT[23..16] - (RO) HW GCR MU BAR Trigger Frame Counter
    SW_BQRP_TRIG_CNT[31..24]     - (RO) HW Bandwidth Query Report Poll Trigger Frame Counter

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TCSR1_SW_BQRP_TRIG_CNT_ADDR             BN1_WF_AGG_TOP_TCSR1_ADDR
#define BN1_WF_AGG_TOP_TCSR1_SW_BQRP_TRIG_CNT_MASK             0xFF000000                // SW_BQRP_TRIG_CNT[31..24]
#define BN1_WF_AGG_TOP_TCSR1_SW_BQRP_TRIG_CNT_SHFT             24
#define BN1_WF_AGG_TOP_TCSR1_SW_GCRMUBAR_TRIG_CNT_ADDR         BN1_WF_AGG_TOP_TCSR1_ADDR
#define BN1_WF_AGG_TOP_TCSR1_SW_GCRMUBAR_TRIG_CNT_MASK         0x00FF0000                // SW_GCRMUBAR_TRIG_CNT[23..16]
#define BN1_WF_AGG_TOP_TCSR1_SW_GCRMUBAR_TRIG_CNT_SHFT         16
#define BN1_WF_AGG_TOP_TCSR1_SW_BSRP_TRIG_CNT_ADDR             BN1_WF_AGG_TOP_TCSR1_ADDR
#define BN1_WF_AGG_TOP_TCSR1_SW_BSRP_TRIG_CNT_MASK             0x0000FF00                // SW_BSRP_TRIG_CNT[15..8]
#define BN1_WF_AGG_TOP_TCSR1_SW_BSRP_TRIG_CNT_SHFT             8
#define BN1_WF_AGG_TOP_TCSR1_HW_MURTS_TRIG_CNT_ADDR            BN1_WF_AGG_TOP_TCSR1_ADDR
#define BN1_WF_AGG_TOP_TCSR1_HW_MURTS_TRIG_CNT_MASK            0x000000FF                // HW_MURTS_TRIG_CNT[7..0]
#define BN1_WF_AGG_TOP_TCSR1_HW_MURTS_TRIG_CNT_SHFT            0

/* =====================================================================================

  ---TCSR2 (0x820f2000 + 0x170)---

    SW_NDPFRP_TRIG_CNT[7..0]     - (RO) HW NDP Feedback Report Poll Trigger Frame Counter
    RESERVED8[30..8]             - (RO) Reserved bits
    TRIG_DBG_CNT_CLR[31]         - (RW) Trigger Frame Counter Clear CR
                                     set 1 to Clear all Trigger Frame Counter

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TCSR2_TRIG_DBG_CNT_CLR_ADDR             BN1_WF_AGG_TOP_TCSR2_ADDR
#define BN1_WF_AGG_TOP_TCSR2_TRIG_DBG_CNT_CLR_MASK             0x80000000                // TRIG_DBG_CNT_CLR[31]
#define BN1_WF_AGG_TOP_TCSR2_TRIG_DBG_CNT_CLR_SHFT             31
#define BN1_WF_AGG_TOP_TCSR2_SW_NDPFRP_TRIG_CNT_ADDR           BN1_WF_AGG_TOP_TCSR2_ADDR
#define BN1_WF_AGG_TOP_TCSR2_SW_NDPFRP_TRIG_CNT_MASK           0x000000FF                // SW_NDPFRP_TRIG_CNT[7..0]
#define BN1_WF_AGG_TOP_TCSR2_SW_NDPFRP_TRIG_CNT_SHFT           0

/* =====================================================================================

  ---AICR0 (0x820f2000 + 0x174)---

    FR_ANT_ID_0[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICR0_FR_ANT_ID_0_ADDR                  BN1_WF_AGG_TOP_AICR0_ADDR
#define BN1_WF_AGG_TOP_AICR0_FR_ANT_ID_0_MASK                  0x00FFFFFF                // FR_ANT_ID_0[23..0]
#define BN1_WF_AGG_TOP_AICR0_FR_ANT_ID_0_SHFT                  0

/* =====================================================================================

  ---AICR1 (0x820f2000 + 0x178)---

    FR_ANT_ID_1[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICR1_FR_ANT_ID_1_ADDR                  BN1_WF_AGG_TOP_AICR1_ADDR
#define BN1_WF_AGG_TOP_AICR1_FR_ANT_ID_1_MASK                  0x00FFFFFF                // FR_ANT_ID_1[23..0]
#define BN1_WF_AGG_TOP_AICR1_FR_ANT_ID_1_SHFT                  0

/* =====================================================================================

  ---AICR2 (0x820f2000 + 0x17C)---

    FR_ANT_ID_2[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICR2_FR_ANT_ID_2_ADDR                  BN1_WF_AGG_TOP_AICR2_ADDR
#define BN1_WF_AGG_TOP_AICR2_FR_ANT_ID_2_MASK                  0x00FFFFFF                // FR_ANT_ID_2[23..0]
#define BN1_WF_AGG_TOP_AICR2_FR_ANT_ID_2_SHFT                  0

/* =====================================================================================

  ---AICR3 (0x820f2000 + 0x180)---

    FR_ANT_ID_3[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICR3_FR_ANT_ID_3_ADDR                  BN1_WF_AGG_TOP_AICR3_ADDR
#define BN1_WF_AGG_TOP_AICR3_FR_ANT_ID_3_MASK                  0x00FFFFFF                // FR_ANT_ID_3[23..0]
#define BN1_WF_AGG_TOP_AICR3_FR_ANT_ID_3_SHFT                  0

/* =====================================================================================

  ---AICR4 (0x820f2000 + 0x184)---

    FR_ANT_ID_4[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICR4_FR_ANT_ID_4_ADDR                  BN1_WF_AGG_TOP_AICR4_ADDR
#define BN1_WF_AGG_TOP_AICR4_FR_ANT_ID_4_MASK                  0x00FFFFFF                // FR_ANT_ID_4[23..0]
#define BN1_WF_AGG_TOP_AICR4_FR_ANT_ID_4_SHFT                  0

/* =====================================================================================

  ---AICR5 (0x820f2000 + 0x188)---

    FR_ANT_ID_5[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICR5_FR_ANT_ID_5_ADDR                  BN1_WF_AGG_TOP_AICR5_ADDR
#define BN1_WF_AGG_TOP_AICR5_FR_ANT_ID_5_MASK                  0x00FFFFFF                // FR_ANT_ID_5[23..0]
#define BN1_WF_AGG_TOP_AICR5_FR_ANT_ID_5_SHFT                  0

/* =====================================================================================

  ---AICR6 (0x820f2000 + 0x18C)---

    FR_ANT_ID_6[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICR6_FR_ANT_ID_6_ADDR                  BN1_WF_AGG_TOP_AICR6_ADDR
#define BN1_WF_AGG_TOP_AICR6_FR_ANT_ID_6_MASK                  0x00FFFFFF                // FR_ANT_ID_6[23..0]
#define BN1_WF_AGG_TOP_AICR6_FR_ANT_ID_6_SHFT                  0

/* =====================================================================================

  ---AICR7 (0x820f2000 + 0x190)---

    FR_ANT_ID_7[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICR7_FR_ANT_ID_7_ADDR                  BN1_WF_AGG_TOP_AICR7_ADDR
#define BN1_WF_AGG_TOP_AICR7_FR_ANT_ID_7_MASK                  0x00FFFFFF                // FR_ANT_ID_7[23..0]
#define BN1_WF_AGG_TOP_AICR7_FR_ANT_ID_7_SHFT                  0

/* =====================================================================================

  ---AICR8 (0x820f2000 + 0x194)---

    FR_ANT_ID_8[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICR8_FR_ANT_ID_8_ADDR                  BN1_WF_AGG_TOP_AICR8_ADDR
#define BN1_WF_AGG_TOP_AICR8_FR_ANT_ID_8_MASK                  0x00FFFFFF                // FR_ANT_ID_8[23..0]
#define BN1_WF_AGG_TOP_AICR8_FR_ANT_ID_8_SHFT                  0

/* =====================================================================================

  ---AICR9 (0x820f2000 + 0x198)---

    FR_ANT_ID_9[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICR9_FR_ANT_ID_9_ADDR                  BN1_WF_AGG_TOP_AICR9_ADDR
#define BN1_WF_AGG_TOP_AICR9_FR_ANT_ID_9_MASK                  0x00FFFFFF                // FR_ANT_ID_9[23..0]
#define BN1_WF_AGG_TOP_AICR9_FR_ANT_ID_9_SHFT                  0

/* =====================================================================================

  ---AICRA (0x820f2000 + 0x19C)---

    FR_ANT_ID_A[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICRA_FR_ANT_ID_A_ADDR                  BN1_WF_AGG_TOP_AICRA_ADDR
#define BN1_WF_AGG_TOP_AICRA_FR_ANT_ID_A_MASK                  0x00FFFFFF                // FR_ANT_ID_A[23..0]
#define BN1_WF_AGG_TOP_AICRA_FR_ANT_ID_A_SHFT                  0

/* =====================================================================================

  ---AICRB (0x820f2000 + 0x200)---

    FR_ANT_ID_B[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICRB_FR_ANT_ID_B_ADDR                  BN1_WF_AGG_TOP_AICRB_ADDR
#define BN1_WF_AGG_TOP_AICRB_FR_ANT_ID_B_MASK                  0x00FFFFFF                // FR_ANT_ID_B[23..0]
#define BN1_WF_AGG_TOP_AICRB_FR_ANT_ID_B_SHFT                  0

/* =====================================================================================

  ---AICRC (0x820f2000 + 0x204)---

    FR_ANT_ID_C[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICRC_FR_ANT_ID_C_ADDR                  BN1_WF_AGG_TOP_AICRC_ADDR
#define BN1_WF_AGG_TOP_AICRC_FR_ANT_ID_C_MASK                  0x00FFFFFF                // FR_ANT_ID_C[23..0]
#define BN1_WF_AGG_TOP_AICRC_FR_ANT_ID_C_SHFT                  0

/* =====================================================================================

  ---AICRD (0x820f2000 + 0x208)---

    FR_ANT_ID_D[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICRD_FR_ANT_ID_D_ADDR                  BN1_WF_AGG_TOP_AICRD_ADDR
#define BN1_WF_AGG_TOP_AICRD_FR_ANT_ID_D_MASK                  0x00FFFFFF                // FR_ANT_ID_D[23..0]
#define BN1_WF_AGG_TOP_AICRD_FR_ANT_ID_D_SHFT                  0

/* =====================================================================================

  ---AICRE (0x820f2000 + 0x20C)---

    FR_ANT_ID_E[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICRE_FR_ANT_ID_E_ADDR                  BN1_WF_AGG_TOP_AICRE_ADDR
#define BN1_WF_AGG_TOP_AICRE_FR_ANT_ID_E_MASK                  0x00FFFFFF                // FR_ANT_ID_E[23..0]
#define BN1_WF_AGG_TOP_AICRE_FR_ANT_ID_E_SHFT                  0

/* =====================================================================================

  ---AICRF (0x820f2000 + 0x210)---

    FR_ANT_ID_F[23..0]           - (RW) Antenna ID for fixed rate TXD is selected by field "ANT_ID_IDX" of TXD
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_AICRF_FR_ANT_ID_F_ADDR                  BN1_WF_AGG_TOP_AICRF_ADDR
#define BN1_WF_AGG_TOP_AICRF_FR_ANT_ID_F_MASK                  0x00FFFFFF                // FR_ANT_ID_F[23..0]
#define BN1_WF_AGG_TOP_AICRF_FR_ANT_ID_F_SHFT                  0

/* =====================================================================================

  ---SCR (0x820f2000 + 0x214)---

    TB_ALLOW_ALL_FRAME_TYPE[0]   - (RW) set 1 to allow all frame type for TB PPDU
    TB_FORCE_FR2AR[1]            - (RW) Set 1 to force TXD from fixed rate to auto rate for TB PPDU
    RESERVED2[31..2]             - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_SCR_TB_FORCE_FR2AR_ADDR                 BN1_WF_AGG_TOP_SCR_ADDR
#define BN1_WF_AGG_TOP_SCR_TB_FORCE_FR2AR_MASK                 0x00000002                // TB_FORCE_FR2AR[1]
#define BN1_WF_AGG_TOP_SCR_TB_FORCE_FR2AR_SHFT                 1
#define BN1_WF_AGG_TOP_SCR_TB_ALLOW_ALL_FRAME_TYPE_ADDR        BN1_WF_AGG_TOP_SCR_ADDR
#define BN1_WF_AGG_TOP_SCR_TB_ALLOW_ALL_FRAME_TYPE_MASK        0x00000001                // TB_ALLOW_ALL_FRAME_TYPE[0]
#define BN1_WF_AGG_TOP_SCR_TB_ALLOW_ALL_FRAME_TYPE_SHFT        0

/* =====================================================================================

  ---SCR0 (0x820f2000 + 0x218)---

    SPARE0[31..0]                - (RW) Spare 0

 =====================================================================================*/
#define BN1_WF_AGG_TOP_SCR0_SPARE0_ADDR                        BN1_WF_AGG_TOP_SCR0_ADDR
#define BN1_WF_AGG_TOP_SCR0_SPARE0_MASK                        0xFFFFFFFF                // SPARE0[31..0]
#define BN1_WF_AGG_TOP_SCR0_SPARE0_SHFT                        0

/* =====================================================================================

  ---SCR1 (0x820f2000 + 0x21c)---

    SPARE1[31..0]                - (RW) Spare 1

 =====================================================================================*/
#define BN1_WF_AGG_TOP_SCR1_SPARE1_ADDR                        BN1_WF_AGG_TOP_SCR1_ADDR
#define BN1_WF_AGG_TOP_SCR1_SPARE1_MASK                        0xFFFFFFFF                // SPARE1[31..0]
#define BN1_WF_AGG_TOP_SCR1_SPARE1_SHFT                        0

/* =====================================================================================

  ---DYNSCR (0x820f2000 + 0x220)---

    DS_EN[31..0]                 - (RW) Enable Dynamic Sounding Function.
                                     Each bit is mapped to 1 entry in WLAN entry. If the entries are absent (i.e. STA mode does not have WLAN entry 33~255), the mapping bits will be invalid.

 =====================================================================================*/
#define BN1_WF_AGG_TOP_DYNSCR_DS_EN_ADDR                       BN1_WF_AGG_TOP_DYNSCR_ADDR
#define BN1_WF_AGG_TOP_DYNSCR_DS_EN_MASK                       0xFFFFFFFF                // DS_EN[31..0]
#define BN1_WF_AGG_TOP_DYNSCR_DS_EN_SHFT                       0

/* =====================================================================================

  ---DYNSSCR (0x820f2000 + 0x240)---

    DS_STATUS[31..0]             - (RW) Dynamic Sounding status. SW read this status to get which peer need to re-sounding for SU.
                                     Each bit is mapped to 1 entry in WLAN entry. If the entries are absent (i.e. STA mode does not have WLAN entry 33~255), the mapping bits will be invalid.

 =====================================================================================*/
#define BN1_WF_AGG_TOP_DYNSSCR_DS_STATUS_ADDR                  BN1_WF_AGG_TOP_DYNSSCR_ADDR
#define BN1_WF_AGG_TOP_DYNSSCR_DS_STATUS_MASK                  0xFFFFFFFF                // DS_STATUS[31..0]
#define BN1_WF_AGG_TOP_DYNSSCR_DS_STATUS_SHFT                  0

/* =====================================================================================

  ---CTETCR (0x820f2000 + 0x260)---

    VHT_EXTRA_TXTIME[7..0]       - (RW) VHT/HE Single MPDU Extra TXTime(unit us)
    VHT_EXTRA_TXTIME_THRESHOLD[15..8] - (RW) VHT/HE Single MPDU Extra TXTime Threshold(unit: 128bytes)
                                     If MPDU len > this threshold, add extra tx time(VHT_EXTRA_TXTIME) into this ppdu.
    RESERVED16[31..16]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_CTETCR_VHT_EXTRA_TXTIME_THRESHOLD_ADDR  BN1_WF_AGG_TOP_CTETCR_ADDR
#define BN1_WF_AGG_TOP_CTETCR_VHT_EXTRA_TXTIME_THRESHOLD_MASK  0x0000FF00                // VHT_EXTRA_TXTIME_THRESHOLD[15..8]
#define BN1_WF_AGG_TOP_CTETCR_VHT_EXTRA_TXTIME_THRESHOLD_SHFT  8
#define BN1_WF_AGG_TOP_CTETCR_VHT_EXTRA_TXTIME_ADDR            BN1_WF_AGG_TOP_CTETCR_ADDR
#define BN1_WF_AGG_TOP_CTETCR_VHT_EXTRA_TXTIME_MASK            0x000000FF                // VHT_EXTRA_TXTIME[7..0]
#define BN1_WF_AGG_TOP_CTETCR_VHT_EXTRA_TXTIME_SHFT            0

/* =====================================================================================

  ---TCCR (0x820f2000 + 0x264)---

    BW_MISMATCH_RLS_TXCMD[0]     - (RW) Release TXCMD if TXCMD bandwidth requirement is mismatch with air bandwidth.
                                     0: defer TXCMD to next backoff timeout
                                     1: release TXCMD
    RESERVED1[31..1]             - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TCCR_BW_MISMATCH_RLS_TXCMD_ADDR         BN1_WF_AGG_TOP_TCCR_ADDR
#define BN1_WF_AGG_TOP_TCCR_BW_MISMATCH_RLS_TXCMD_MASK         0x00000001                // BW_MISMATCH_RLS_TXCMD[0]
#define BN1_WF_AGG_TOP_TCCR_BW_MISMATCH_RLS_TXCMD_SHFT         0

/* =====================================================================================

  ---DCR (0x820f2000 + 0x2e0)---

    DBG_EXTRA_SEL0[5..0]         - (RW) Debug extra selector.
    RESERVED6[7..6]              - (RO) Reserved bits
    DBG_EXTRA_SEL1[13..8]        - (RW) Debug extra selector.
    RESERVED14[15..14]           - (RO) Reserved bits
    DBG_EXTRA_SEL2[21..16]       - (RW) Debug extra selector.
    RESERVED22[23..22]           - (RO) Reserved bits
    DBG_EXTRA_SEL3[29..24]       - (RW) Debug extra selector.
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_DCR_DBG_EXTRA_SEL3_ADDR                 BN1_WF_AGG_TOP_DCR_ADDR
#define BN1_WF_AGG_TOP_DCR_DBG_EXTRA_SEL3_MASK                 0x3F000000                // DBG_EXTRA_SEL3[29..24]
#define BN1_WF_AGG_TOP_DCR_DBG_EXTRA_SEL3_SHFT                 24
#define BN1_WF_AGG_TOP_DCR_DBG_EXTRA_SEL2_ADDR                 BN1_WF_AGG_TOP_DCR_ADDR
#define BN1_WF_AGG_TOP_DCR_DBG_EXTRA_SEL2_MASK                 0x003F0000                // DBG_EXTRA_SEL2[21..16]
#define BN1_WF_AGG_TOP_DCR_DBG_EXTRA_SEL2_SHFT                 16
#define BN1_WF_AGG_TOP_DCR_DBG_EXTRA_SEL1_ADDR                 BN1_WF_AGG_TOP_DCR_ADDR
#define BN1_WF_AGG_TOP_DCR_DBG_EXTRA_SEL1_MASK                 0x00003F00                // DBG_EXTRA_SEL1[13..8]
#define BN1_WF_AGG_TOP_DCR_DBG_EXTRA_SEL1_SHFT                 8
#define BN1_WF_AGG_TOP_DCR_DBG_EXTRA_SEL0_ADDR                 BN1_WF_AGG_TOP_DCR_ADDR
#define BN1_WF_AGG_TOP_DCR_DBG_EXTRA_SEL0_MASK                 0x0000003F                // DBG_EXTRA_SEL0[5..0]
#define BN1_WF_AGG_TOP_DCR_DBG_EXTRA_SEL0_SHFT                 0

/* =====================================================================================

  ---SMDCR (0x820f2000 + 0x2e4)---

    SMDBG_EXTRA_SEL0[5..0]       - (RW) State Machine Debug extra selector.
    RESERVED6[7..6]              - (RO) Reserved bits
    SMDBG_EXTRA_SEL1[13..8]      - (RW) State Machine Debug extra selector.
    RESERVED14[15..14]           - (RO) Reserved bits
    SMDBG_EXTRA_SEL2[21..16]     - (RW) State Machine Debug extra selector.
    RESERVED22[23..22]           - (RO) Reserved bits
    SMDBG_EXTRA_SEL3[29..24]     - (RW) State Machine Debug extra selector.
    RESERVED30[31..30]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_SMDCR_SMDBG_EXTRA_SEL3_ADDR             BN1_WF_AGG_TOP_SMDCR_ADDR
#define BN1_WF_AGG_TOP_SMDCR_SMDBG_EXTRA_SEL3_MASK             0x3F000000                // SMDBG_EXTRA_SEL3[29..24]
#define BN1_WF_AGG_TOP_SMDCR_SMDBG_EXTRA_SEL3_SHFT             24
#define BN1_WF_AGG_TOP_SMDCR_SMDBG_EXTRA_SEL2_ADDR             BN1_WF_AGG_TOP_SMDCR_ADDR
#define BN1_WF_AGG_TOP_SMDCR_SMDBG_EXTRA_SEL2_MASK             0x003F0000                // SMDBG_EXTRA_SEL2[21..16]
#define BN1_WF_AGG_TOP_SMDCR_SMDBG_EXTRA_SEL2_SHFT             16
#define BN1_WF_AGG_TOP_SMDCR_SMDBG_EXTRA_SEL1_ADDR             BN1_WF_AGG_TOP_SMDCR_ADDR
#define BN1_WF_AGG_TOP_SMDCR_SMDBG_EXTRA_SEL1_MASK             0x00003F00                // SMDBG_EXTRA_SEL1[13..8]
#define BN1_WF_AGG_TOP_SMDCR_SMDBG_EXTRA_SEL1_SHFT             8
#define BN1_WF_AGG_TOP_SMDCR_SMDBG_EXTRA_SEL0_ADDR             BN1_WF_AGG_TOP_SMDCR_ADDR
#define BN1_WF_AGG_TOP_SMDCR_SMDBG_EXTRA_SEL0_MASK             0x0000003F                // SMDBG_EXTRA_SEL0[5..0]
#define BN1_WF_AGG_TOP_SMDCR_SMDBG_EXTRA_SEL0_SHFT             0

/* =====================================================================================

  ---TXCMDSMCR (0x820f2000 + 0x2e8)---

    TXCMD_CS[2..0]               - (RO) Current state of TXCMD
    RESERVED3[3]                 - (RO) Reserved bits
    ADDIFD_CS[6..4]              - (RO) Current state of TXCMD ADDIFD
    RESERVED7[7]                 - (RO) Reserved bits
    RPT_CS[10..8]                - (RO) Current state of CMDRPT
    RESERVED11[11]               - (RO) Reserved bits
    BAR_CS[13..12]               - (RO) Current state of BAR
    RESERVED14[31..14]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_TXCMDSMCR_BAR_CS_ADDR                   BN1_WF_AGG_TOP_TXCMDSMCR_ADDR
#define BN1_WF_AGG_TOP_TXCMDSMCR_BAR_CS_MASK                   0x00003000                // BAR_CS[13..12]
#define BN1_WF_AGG_TOP_TXCMDSMCR_BAR_CS_SHFT                   12
#define BN1_WF_AGG_TOP_TXCMDSMCR_RPT_CS_ADDR                   BN1_WF_AGG_TOP_TXCMDSMCR_ADDR
#define BN1_WF_AGG_TOP_TXCMDSMCR_RPT_CS_MASK                   0x00000700                // RPT_CS[10..8]
#define BN1_WF_AGG_TOP_TXCMDSMCR_RPT_CS_SHFT                   8
#define BN1_WF_AGG_TOP_TXCMDSMCR_ADDIFD_CS_ADDR                BN1_WF_AGG_TOP_TXCMDSMCR_ADDR
#define BN1_WF_AGG_TOP_TXCMDSMCR_ADDIFD_CS_MASK                0x00000070                // ADDIFD_CS[6..4]
#define BN1_WF_AGG_TOP_TXCMDSMCR_ADDIFD_CS_SHFT                4
#define BN1_WF_AGG_TOP_TXCMDSMCR_TXCMD_CS_ADDR                 BN1_WF_AGG_TOP_TXCMDSMCR_ADDR
#define BN1_WF_AGG_TOP_TXCMDSMCR_TXCMD_CS_MASK                 0x00000007                // TXCMD_CS[2..0]
#define BN1_WF_AGG_TOP_TXCMDSMCR_TXCMD_CS_SHFT                 0

/* =====================================================================================

  ---SMCR0 (0x820f2000 + 0x2f0)---

    SRCH_CS0[3..0]               - (RO) Current state of SRCH depend on SMDBG_EXTRA_SEL0
    PS_CS0[6..4]                 - (RO) Current state of PROSTS depend on SMDBG_EXTRA_SEL0
    RESERVED7[7]                 - (RO) Reserved bits
    PP_CS0[10..8]                - (RO) Current state of PDUPRE depend on SMDBG_EXTRA_SEL0
    RESERVED11[11]               - (RO) Reserved bits
    AGG_CS0[14..12]              - (RO) Current state of AGG depend on SMDBG_EXTRA_SEL0
    RESERVED15[15]               - (RO) Reserved bits
    FTMPDU_CS0[17..16]           - (RO) Current state of FTMPDU depend on SMDBG_EXTRA_SEL0
    RESERVED18[19..18]           - (RO) Reserved bits
    FTWTBL_CS0[21..20]           - (RO) Current state of FTWTBL depend on SMDBG_EXTRA_SEL0
    RESERVED22[31..22]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_SMCR0_FTWTBL_CS0_ADDR                   BN1_WF_AGG_TOP_SMCR0_ADDR
#define BN1_WF_AGG_TOP_SMCR0_FTWTBL_CS0_MASK                   0x00300000                // FTWTBL_CS0[21..20]
#define BN1_WF_AGG_TOP_SMCR0_FTWTBL_CS0_SHFT                   20
#define BN1_WF_AGG_TOP_SMCR0_FTMPDU_CS0_ADDR                   BN1_WF_AGG_TOP_SMCR0_ADDR
#define BN1_WF_AGG_TOP_SMCR0_FTMPDU_CS0_MASK                   0x00030000                // FTMPDU_CS0[17..16]
#define BN1_WF_AGG_TOP_SMCR0_FTMPDU_CS0_SHFT                   16
#define BN1_WF_AGG_TOP_SMCR0_AGG_CS0_ADDR                      BN1_WF_AGG_TOP_SMCR0_ADDR
#define BN1_WF_AGG_TOP_SMCR0_AGG_CS0_MASK                      0x00007000                // AGG_CS0[14..12]
#define BN1_WF_AGG_TOP_SMCR0_AGG_CS0_SHFT                      12
#define BN1_WF_AGG_TOP_SMCR0_PP_CS0_ADDR                       BN1_WF_AGG_TOP_SMCR0_ADDR
#define BN1_WF_AGG_TOP_SMCR0_PP_CS0_MASK                       0x00000700                // PP_CS0[10..8]
#define BN1_WF_AGG_TOP_SMCR0_PP_CS0_SHFT                       8
#define BN1_WF_AGG_TOP_SMCR0_PS_CS0_ADDR                       BN1_WF_AGG_TOP_SMCR0_ADDR
#define BN1_WF_AGG_TOP_SMCR0_PS_CS0_MASK                       0x00000070                // PS_CS0[6..4]
#define BN1_WF_AGG_TOP_SMCR0_PS_CS0_SHFT                       4
#define BN1_WF_AGG_TOP_SMCR0_SRCH_CS0_ADDR                     BN1_WF_AGG_TOP_SMCR0_ADDR
#define BN1_WF_AGG_TOP_SMCR0_SRCH_CS0_MASK                     0x0000000F                // SRCH_CS0[3..0]
#define BN1_WF_AGG_TOP_SMCR0_SRCH_CS0_SHFT                     0

/* =====================================================================================

  ---SMCR1 (0x820f2000 + 0x2f4)---

    SRCH_CS1[3..0]               - (RO) Current state of SRCH depend on SMDBG_EXTRA_SEL1
    PS_CS1[6..4]                 - (RO) Current state of PROSTS depend on SMDBG_EXTRA_SEL1
    RESERVED7[7]                 - (RO) Reserved bits
    PP_CS1[10..8]                - (RO) Current state of PDUPRE depend on SMDBG_EXTRA_SEL1
    RESERVED11[11]               - (RO) Reserved bits
    AGG_CS1[14..12]              - (RO) Current state of AGG depend on SMDBG_EXTRA_SEL1
    RESERVED15[15]               - (RO) Reserved bits
    FTMPDU_CS1[17..16]           - (RO) Current state of FTMPDU depend on SMDBG_EXTRA_SEL1
    RESERVED18[19..18]           - (RO) Reserved bits
    FTWTBL_CS1[21..20]           - (RO) Current state of FTWTBL depend on SMDBG_EXTRA_SEL1
    RESERVED22[31..22]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_SMCR1_FTWTBL_CS1_ADDR                   BN1_WF_AGG_TOP_SMCR1_ADDR
#define BN1_WF_AGG_TOP_SMCR1_FTWTBL_CS1_MASK                   0x00300000                // FTWTBL_CS1[21..20]
#define BN1_WF_AGG_TOP_SMCR1_FTWTBL_CS1_SHFT                   20
#define BN1_WF_AGG_TOP_SMCR1_FTMPDU_CS1_ADDR                   BN1_WF_AGG_TOP_SMCR1_ADDR
#define BN1_WF_AGG_TOP_SMCR1_FTMPDU_CS1_MASK                   0x00030000                // FTMPDU_CS1[17..16]
#define BN1_WF_AGG_TOP_SMCR1_FTMPDU_CS1_SHFT                   16
#define BN1_WF_AGG_TOP_SMCR1_AGG_CS1_ADDR                      BN1_WF_AGG_TOP_SMCR1_ADDR
#define BN1_WF_AGG_TOP_SMCR1_AGG_CS1_MASK                      0x00007000                // AGG_CS1[14..12]
#define BN1_WF_AGG_TOP_SMCR1_AGG_CS1_SHFT                      12
#define BN1_WF_AGG_TOP_SMCR1_PP_CS1_ADDR                       BN1_WF_AGG_TOP_SMCR1_ADDR
#define BN1_WF_AGG_TOP_SMCR1_PP_CS1_MASK                       0x00000700                // PP_CS1[10..8]
#define BN1_WF_AGG_TOP_SMCR1_PP_CS1_SHFT                       8
#define BN1_WF_AGG_TOP_SMCR1_PS_CS1_ADDR                       BN1_WF_AGG_TOP_SMCR1_ADDR
#define BN1_WF_AGG_TOP_SMCR1_PS_CS1_MASK                       0x00000070                // PS_CS1[6..4]
#define BN1_WF_AGG_TOP_SMCR1_PS_CS1_SHFT                       4
#define BN1_WF_AGG_TOP_SMCR1_SRCH_CS1_ADDR                     BN1_WF_AGG_TOP_SMCR1_ADDR
#define BN1_WF_AGG_TOP_SMCR1_SRCH_CS1_MASK                     0x0000000F                // SRCH_CS1[3..0]
#define BN1_WF_AGG_TOP_SMCR1_SRCH_CS1_SHFT                     0

/* =====================================================================================

  ---SMCR2 (0x820f2000 + 0x2f8)---

    SRCH_CS2[3..0]               - (RO) Current state of SRCH depend on SMDBG_EXTRA_SEL2
    PS_CS2[6..4]                 - (RO) Current state of PROSTS depend on SMDBG_EXTRA_SEL2
    RESERVED7[7]                 - (RO) Reserved bits
    PP_CS2[10..8]                - (RO) Current state of PDUPRE depend on SMDBG_EXTRA_SEL2
    RESERVED11[11]               - (RO) Reserved bits
    AGG_CS2[14..12]              - (RO) Current state of AGG depend on SMDBG_EXTRA_SEL2
    RESERVED15[15]               - (RO) Reserved bits
    FTMPDU_CS2[17..16]           - (RO) Current state of FTMPDU depend on SMDBG_EXTRA_SEL2
    RESERVED18[19..18]           - (RO) Reserved bits
    FTWTBL_CS2[21..20]           - (RO) Current state of FTWTBL depend on SMDBG_EXTRA_SEL2
    RESERVED22[31..22]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_SMCR2_FTWTBL_CS2_ADDR                   BN1_WF_AGG_TOP_SMCR2_ADDR
#define BN1_WF_AGG_TOP_SMCR2_FTWTBL_CS2_MASK                   0x00300000                // FTWTBL_CS2[21..20]
#define BN1_WF_AGG_TOP_SMCR2_FTWTBL_CS2_SHFT                   20
#define BN1_WF_AGG_TOP_SMCR2_FTMPDU_CS2_ADDR                   BN1_WF_AGG_TOP_SMCR2_ADDR
#define BN1_WF_AGG_TOP_SMCR2_FTMPDU_CS2_MASK                   0x00030000                // FTMPDU_CS2[17..16]
#define BN1_WF_AGG_TOP_SMCR2_FTMPDU_CS2_SHFT                   16
#define BN1_WF_AGG_TOP_SMCR2_AGG_CS2_ADDR                      BN1_WF_AGG_TOP_SMCR2_ADDR
#define BN1_WF_AGG_TOP_SMCR2_AGG_CS2_MASK                      0x00007000                // AGG_CS2[14..12]
#define BN1_WF_AGG_TOP_SMCR2_AGG_CS2_SHFT                      12
#define BN1_WF_AGG_TOP_SMCR2_PP_CS2_ADDR                       BN1_WF_AGG_TOP_SMCR2_ADDR
#define BN1_WF_AGG_TOP_SMCR2_PP_CS2_MASK                       0x00000700                // PP_CS2[10..8]
#define BN1_WF_AGG_TOP_SMCR2_PP_CS2_SHFT                       8
#define BN1_WF_AGG_TOP_SMCR2_PS_CS2_ADDR                       BN1_WF_AGG_TOP_SMCR2_ADDR
#define BN1_WF_AGG_TOP_SMCR2_PS_CS2_MASK                       0x00000070                // PS_CS2[6..4]
#define BN1_WF_AGG_TOP_SMCR2_PS_CS2_SHFT                       4
#define BN1_WF_AGG_TOP_SMCR2_SRCH_CS2_ADDR                     BN1_WF_AGG_TOP_SMCR2_ADDR
#define BN1_WF_AGG_TOP_SMCR2_SRCH_CS2_MASK                     0x0000000F                // SRCH_CS2[3..0]
#define BN1_WF_AGG_TOP_SMCR2_SRCH_CS2_SHFT                     0

/* =====================================================================================

  ---SMCR3 (0x820f2000 + 0x2fc)---

    SRCH_CS3[3..0]               - (RO) Current state of SRCH depend on SMDBG_EXTRA_SEL3
    PS_CS3[6..4]                 - (RO) Current state of PROSTS depend on SMDBG_EXTRA_SEL3
    RESERVED7[7]                 - (RO) Reserved bits
    PP_CS3[10..8]                - (RO) Current state of PDUPRE depend on SMDBG_EXTRA_SEL3
    RESERVED11[11]               - (RO) Reserved bits
    AGG_CS3[14..12]              - (RO) Current state of AGG depend on SMDBG_EXTRA_SEL3
    RESERVED15[15]               - (RO) Reserved bits
    FTMPDU_CS3[17..16]           - (RO) Current state of FTMPDU depend on SMDBG_EXTRA_SEL3
    RESERVED18[19..18]           - (RO) Reserved bits
    FTWTBL_CS3[21..20]           - (RO) Current state of FTWTBL depend on SMDBG_EXTRA_SEL3
    RESERVED22[31..22]           - (RO) Reserved bits

 =====================================================================================*/
#define BN1_WF_AGG_TOP_SMCR3_FTWTBL_CS3_ADDR                   BN1_WF_AGG_TOP_SMCR3_ADDR
#define BN1_WF_AGG_TOP_SMCR3_FTWTBL_CS3_MASK                   0x00300000                // FTWTBL_CS3[21..20]
#define BN1_WF_AGG_TOP_SMCR3_FTWTBL_CS3_SHFT                   20
#define BN1_WF_AGG_TOP_SMCR3_FTMPDU_CS3_ADDR                   BN1_WF_AGG_TOP_SMCR3_ADDR
#define BN1_WF_AGG_TOP_SMCR3_FTMPDU_CS3_MASK                   0x00030000                // FTMPDU_CS3[17..16]
#define BN1_WF_AGG_TOP_SMCR3_FTMPDU_CS3_SHFT                   16
#define BN1_WF_AGG_TOP_SMCR3_AGG_CS3_ADDR                      BN1_WF_AGG_TOP_SMCR3_ADDR
#define BN1_WF_AGG_TOP_SMCR3_AGG_CS3_MASK                      0x00007000                // AGG_CS3[14..12]
#define BN1_WF_AGG_TOP_SMCR3_AGG_CS3_SHFT                      12
#define BN1_WF_AGG_TOP_SMCR3_PP_CS3_ADDR                       BN1_WF_AGG_TOP_SMCR3_ADDR
#define BN1_WF_AGG_TOP_SMCR3_PP_CS3_MASK                       0x00000700                // PP_CS3[10..8]
#define BN1_WF_AGG_TOP_SMCR3_PP_CS3_SHFT                       8
#define BN1_WF_AGG_TOP_SMCR3_PS_CS3_ADDR                       BN1_WF_AGG_TOP_SMCR3_ADDR
#define BN1_WF_AGG_TOP_SMCR3_PS_CS3_MASK                       0x00000070                // PS_CS3[6..4]
#define BN1_WF_AGG_TOP_SMCR3_PS_CS3_SHFT                       4
#define BN1_WF_AGG_TOP_SMCR3_SRCH_CS3_ADDR                     BN1_WF_AGG_TOP_SMCR3_ADDR
#define BN1_WF_AGG_TOP_SMCR3_SRCH_CS3_MASK                     0x0000000F                // SRCH_CS3[3..0]
#define BN1_WF_AGG_TOP_SMCR3_SRCH_CS3_SHFT                     0

#ifdef __cplusplus
}
#endif

#endif // __BN1_WF_AGG_TOP_REGS_H__
